Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

High dynamic synchronization algorithm based on cyclic spectral density

A new high dynamic synchronization algorithm using cyclic spectral density was presented according to the theories of cyclic spectral density and its anti-interface and anti-noise properties.The closed forms of frequency error and phase error were obtained,and their performances were analyzed.The in-phase signal throw costas loop was normalized to obtain a cosine signal.Cyclic spectral density of the cosine signal of was computed to obtain the frequency error and the phase error and then results were put into NCO to synchronize.Finally,the performance of the presented algorithms was compared with the conventional algorithms by virtue of simulations,and the simulation results proved the correctness and the superiority of the new algorithms.

电网故障下含直驱风电机组的电力系统频率动态响应分析

电网受扰后基于模型解析的频率响应分析对电力系统安全评估与紧急控制具有重要意义。电网发生故障时,直驱风电机组(DDWT)并网点电压幅值跌落引发控制器暂态响应,同时电压相位突变引发锁相暂态响应,锁相暂态响应又通过变流器控制传导产生功率控制误差,可能导致现有以负荷突变场景为对象的频率特性分析产生较大偏差。为此,提出了电网故障下DDWT锁相偏差的量化方法;解析了锁相偏差经DDWT变流器控制的传导路径,提出了锁相暂态响应导致DDWT功率控制误差的机理及其计算方法;建立了电网故障下含DDWT的电力系统频率响应模型,提出了锁相暂态响应影响下系统频率变化率和最大频率偏差的计算方法,解析了电网故障下考虑DDWT功率控制误差的电力系统频率动态响应特性,并通过算例分析验证了所提方法的有效性。

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

CP-PLL快速入锁集成电路方案设计

该文基于TSMC 0.18μm RF CMOS工艺实现了一个用于加快CP-PLL锁定时间的数模混合复合结构,该复合结构主要包括两个独立单元——动态环路带宽单元及预置位反馈环。其中,两个单元的控制电路均采用全数字电路实现,并通过DC综合与ICC自动布局布线得到版图信息。经过同一CP-PLL参数环境下的对比分析,比较了包括传统结构的3种方案的锁定时间。在工作电源1.8 V下,优化后的锁定时间为1.12μs,较传统结构锁定时间提升了76.7%;整体相噪在稳态保持-103.1 dBc/Hz@1 MHz,较传统结构仅上升了0.3%。证明该复合结构能够有效降低上电启动以及跳频时的锁定时间。

一种基于FLL和PLL的复合载波环的跟踪精度分析

基于卫星通信高动态、高精度的需求,提出了一种锁频环与锁相环相结合的双环载波跟踪系统。通过分析热噪声和动态应力对载波环跟踪精度的影响,指出了锁相环和锁频环的优缺点,给出了复合载波环的结构框图和工作流程。最后通过系统仿真,证明了复合载波环比单一载波环具有更全面的性能。

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.

GPS接收机PLL与卡尔曼跟踪环路性能分析

本文重点研究传统PLL环路和卡尔曼跟踪环路理论性能分析方法,理论上分析比较两种跟踪环路的跟踪灵敏度和动态应力性能,并通过GPS软件接收机仿真验证得出结论,相对于PLL环路,卡尔曼跟踪环路灵敏度最大可提高3d B左右,动态性能最大可提高27g/s左右。

A Novel PLL Structure for Dynamic Stability Improvement of DFIG-based Wind Energy Generation Systems During Asymmetric LVRT

The dynamic coupling effect,which is introduced by the dual-sequence phase-locked loops(PLLs)used in doublyfed induction generator(DFIG)based wind energy generation systems(WEGSs)during asymmetric low voltage ride-through(LVRT)in weak grid,needs attention.In order to study this new dynamic coupling effect,an equivalent two-degree-of-freedom(2-DOF)spring damper particle model is used in this paper to develop a small-signal model for the dual-sequence PLLs.The dynamic interaction between the positive-sequence(PS)and negative-sequence(NS)PLLs is unveiled.Moreover,the impact of the dynamic coupling between the dual-sequence PLLs on the dynamic stability during the steady-state stage of an asymmetric fault is analyzed.The analysis results show that the dynamic coupling between the dual-sequence PLLs will cause drift in the frequency and damping for the PS and NS PLL modes.This will change the instability modal of the system and introduce the risk of dynamic instability.Hence,the effectiveness of existing control strategies for enhancing the dynamic stability will be decreased.Finally,a novel PLL structure is designed to improve the dynamic stability of the system during the steady-state stage of an asymmetric fault.The effectiveness of the proposed strategy is verified by simulations and experiments.

Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.

MLE辅助PLL的高动态GPS载波跟踪

针对传统锁频环(FLL)鉴别器存在一步延迟效应和近似误差的问题,提出一种基于极大似然估计器(MLE)辅助锁相环(PLL)的高动态载波跟踪环路。该方法从极大似然估计理论入手,构造多普勒频移的非相干极大似然代价函数,采用非迭代估计方法求取各通道多普勒频移偏差的极大似然估计,与PLL进行融合滤波并计算频率修正量,进而控制本地数控振荡器(NCO)完成载波跟踪。仿真结果表明:在同等环路阶数和滤波器带宽条件下,新方法的响应速度、动态忍受力优于基于FLL辅助PLL的方法,可以跟踪加加速度达到100g/s的超高动态信号。

电压不平衡跌落时动态电压恢复器的快速PLL策略

传统的锁相环(PLL)算法不能满足动态电压恢复器(DVR)在三相电压不平衡故障时的快速准确锁相要求。在分析传统PLL的基础上,提出了dαβ-PLL和"推演顺接"相结合的锁相策略。新的锁相策略在电压跌落开始的第一个周波T(20 ms)内基于历史数据进行推演并锁定相位;一个周波之后采用dαβ-PLL来锁定相位。仿真结果与样机试验验证了新型PLL锁相策略在三相电压不平衡跌落故障时能够快速准确锁相,可以满足DVR的使用要求。

Tracking error analysis and simulation of FLL-assisted PLL

In order to solve problems in high dynamic environment, a frequency-locked loop （FLL） assisted phase-locked loop （PLL） is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter

This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

Comparative Study of Single-phase Phase-locked Loops for Grid-connected Inverters Under Non-ideal Grid Conditions

In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.

锁相环同步VSC接入弱网下的低频动态稳定性分析模型与机理研究

基于锁相环(PLL)同步接入弱网的电压源型换流器(WG-VSC)存在由“外环-PLL-弱网”交互主导的低频动态(LFD)稳定问题。为清晰揭示各关键环节及其交互对WG-VSC的LFD影响机理,提出一种等效PLL模型。首先建立了适用于多种典型外环控制模式的WG-VSC的LFD分析的基本模型,该模型包含原PLL环节及耦合了外环、电网强度及VSC运行点信息的“外环-弱网”环节。其次,将“外环-弱网”环节划分为有功侧外环对PLL的影响路径及无功侧外环所引入的对PLL的影响路径,以清晰表征VSC外环与PLL的交互关系。然后,基于LFD主导模态将“外环-弱网”环节简化为一阶环节,并结合原PLL的PI控制环节,得到保持足够LFD分析精度的二阶等效PLL模型,并基于该模型分析和揭示了“外环-PLL-弱网”的交互对WG-VSC的LFD的影响机理。最后,基于详细开关模型的时域仿真结果验证了等效PLL模型的有效性和分析结果的准确性。

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.