Vein visualization enhancement by dual-wavelength phase-locked denoising technology

Visual near-infrared imaging equipment has broad applications in various fields such as venipuncture,facial injections,and safety verification due to its noncontact,compact,and portable design.Currently,most studies utilize near-infrared single-wavelength for image acquisition of veins.However,many substances in the skin,including water,protein,and melanin can create significant background noise,which hinders accurate detection.In this paper,we developed a dual-wavelength imaging system with phase-locked denoising technology to acquire vein image.The signals in the effective region are compared by using the absorption valley and peak of hemoglobin at 700nm and 940nm,respectively.The phase-locked denoising algorithm is applied to decrease the noise and interference of complex surroundings from the images.The imaging results of the vein are successfully extracted in complex noise environment.It is demonstrated that the denoising effect on hand veins imaging can be improved with 57.3%by using our dual-wavelength phase-locked denoising technology.Consequently,this work proposes a novel approach for venous imaging with dual-wavelengths and phase-locked denoising algorithm to extract venous imaging results in complex noisy environment better.

Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

Adaptive Robust Servo Control for Vertical Electric Stabilization System of Tank and Experimental Validation

A tracking stability control problem for the vertical electric stabilization system of moving tank based on adaptive robust servo control is addressed.This paper mainly focuses on two types of possibly fast timevarying but bounded uncertainty within the vertical electric stabilization system:model parameter uncertainty and uncertain nonlinearity.First,the vertical electric stabilization system is constructed as an uncertain nonlinear dynamic system that can reflect the practical mechanics transfer process of the system.Second,the dynamical equation in the form of state space is established by designing the angular tracking error.Third,the comprehensive parameter of system uncertainty is designed to estimate the most conservative effects of uncertainty.Finally,an adaptive robust servo control which can effectively handle the combined effects of complex nonlinearity and uncertainty is proposed.The feasibility of the proposed control strategy under the practical physical condition is validated through the tests on the experimental platform.This paper pioneers the introduction of the internal nonlinearity and uncertainty of the vertical electric stabilization system into the settlement of the tracking stability control problem,and validates the advanced servo control strategy through experiment for the first time.

Research and Application of"Soft"Devices for Realizing Servo Amplification

This article analyzes and discusses the working principle and problems encountered by various servo amplification devices used in the on-site continuous adjustment system,analyzes and discusses the application of the servo mechanism,and analyzes the mechanism of the servo device's implementation of the"positioning"func-tion on the control device.Intended to guide the continuous adjustment process in controlling the function/accuracy of actuator equipment and application debugging,ensuring the safe and stable operation of production equipment and facilities.

Fourier Spectrometer based on Wide-range and Phase-locked Michelson Interferometer with Femtosecond Laser Excitation

A wide-range and phase-locked Michelson interferometer technique is described. This technique combined with femtosecond laser is used to measure the spectrum of the rare-earth ion Nd：YVO4, which presents very high signal to noise ratio of interferometric intensity output and higher spectral resolution than traditional grating spectrophotometer.

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

Tunable characteristic of phase-locked quantum cascade laser arrays

A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

PHASE-LOCKED 2-D JOSEPHSON JUNCTION ARRAYS AS SUBMILLIMETER OSCILLATORS

This letter presents the results of numerical simulations for phase-locked 2-D Joseph-son junction array oscillator. The simulation result shows that the junctions of 2-D array can mutually phase-locked in a considerable area if the parameters can be carefully selected. The oscillators are formed with up to 33 identical Nb/AIOx/Nb junctions, and the junctions are connected with Nb microstrip resonators. Optimum structure parameters for oscillator circuit design can be obtained with these simulation results.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Backstepping Sliding Mode Control Based on Extended State Observer for Hydraulic Servo System

Hydraulic servo system plays an important role in industrial fields due to the advantages of high response,small size-to-power ratio and large driving force.However,inherent nonlinear behaviors and modeling uncertainties are the main obstacles for hydraulic servo system to achieve high tracking perfor-mance.To deal with these difficulties,this paper presents a backstepping sliding mode controller to improve the dynamic tracking performance and anti-interfer-ence ability.For this purpose,the nonlinear dynamic model is firstly established,where the nonlinear behaviors and modeling uncertainties are lumped as one term.Then,the extended state observer is introduced to estimate the lumped distur-bance.The system stability is proved by using the Lyapunov stability theorem.Finally,comparative simulation and experimental are conducted on a hydraulic servo system platform to verify the efficiency of the proposed control scheme.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Observation of Phase-Locked States in the Atlantic Multi-Decadal Oscillation(AMO)

We report that the Atlantic Multi-Decadal Oscillation (AMO) shows the same phase-locked states of period 2 and 3 years that have been reported in many other climate indices. In addition, we find that the report by Muller, Curry et al. of an oscillation in the AMO of 9.1 years is a misinterpretation of a maximum in the Fourier spectrum.

Output feedback control and parameters influence analysis of active suspension electro-hydraulic servo actuator

The hydraulic servo actuator of heavy vehicle active suspension is investigated to clarify the correlation between system parameters and the control characteristics of active suspension hydraulic servo system.Accordingly, a nonlinear physical model of electro-hydraulic servo active suspension system is built.Compared with the conventional nonlinear modeling, the model in this study considers the asymmetry of working areas caused by single rod hydraulic cylinder in the suspension system.In accordance with the model, a nonlinear output feedback controller based on backstepping is designed, and the effectiveness of the controller is proved based on the experimental platform.The dynamic response curve of the electro-hydraulic servo control system under the change of parameters is generated based on the simulation model.The sensitivity of electro-hydraulic servo control performance to the change of system physical parameters is investigated, and two evaluation indexes are proposed to quantify and compare the effect of all physical parameter changes on position control system.As revealed by the results, the position control characteristics of suspension actuator are more sensitive to the changes of flow gain of the servo valve, system supply oil pressure and effective working areas of cylinder, and the two evaluation indexes are over 10 times higher than other physical parameters.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.