In the emerging Industrial Internet of Things(IIoT),authentication problems have become an urgent issue for massive resource-constrained devices because traditional costly security mechanisms are not suitable for them...In the emerging Industrial Internet of Things(IIoT),authentication problems have become an urgent issue for massive resource-constrained devices because traditional costly security mechanisms are not suitable for them.The security protocol designed for resource-constrained systems should not only be secure but also efficient in terms of usage of energy,storage,and processing.Although recently many lightweight schemes have been proposed,to the best of our knowledge,they are unable to address the problem of privacy preservation with the resistance of Denial of Service(DoS)attacks in a practical way.In this paper,we propose a lightweight authentication protocol based on the Physically Unclonable Function(PUF)to overcome the limitations of existing schemes.The protocol provides an ingenious authentication and synchronization mechanism to solve the contradictions amount forward secrecy,DoS attacks,and resource-constrained.The performance analysis and comparison show that the proposed scheme can better improve the authentication security and efficiency for resource-constrained systems in IIoT.展开更多
IoT devices rely on authentication mechanisms to render secure message exchange.During data transmission,scalability,data integrity,and processing time have been considered challenging aspects for a system constituted...IoT devices rely on authentication mechanisms to render secure message exchange.During data transmission,scalability,data integrity,and processing time have been considered challenging aspects for a system constituted by IoT devices.The application of physical unclonable functions(PUFs)ensures secure data transmission among the internet of things(IoT)devices in a simplified network with an efficient time-stamped agreement.This paper proposes a secure,lightweight,cost-efficient reinforcement machine learning framework(SLCR-MLF)to achieve decentralization and security,thus enabling scalability,data integrity,and optimized processing time in IoT devices.PUF has been integrated into SLCR-MLF to improve the security of the cluster head node in the IoT platform during transmission by providing the authentication service for device-to-device communication.An IoT network gathers information of interest from multiple cluster members selected by the proposed framework.In addition,the software-defined secured(SDS)technique is integrated with SLCR-MLF to improve data integrity and optimize processing time in the IoT platform.Simulation analysis shows that the proposed framework outperforms conventional methods regarding the network’s lifetime,energy,secured data retrieval rate,and performance ratio.By enabling the proposed framework,number of residual nodes is reduced to 16%,energy consumption is reduced by up to 50%,almost 30%improvement in data retrieval rate,and network lifetime is improved by up to 1000 msec.展开更多
Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intell...Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.展开更多
In order to reduce physical unclonable fixnction (PUF) response instability and imbalance caused by the metastability and the bias of arbiter, this paper uses an improved balanced D flip-plop (DFF) based on the un...In order to reduce physical unclonable fixnction (PUF) response instability and imbalance caused by the metastability and the bias of arbiter, this paper uses an improved balanced D flip-plop (DFF) based on the unbalanced DFF to reduce the bias in response output and enhances the security of PUF by adopting two balanced DFFs in series. The experimental results show that two cascaded balanced DFFs improve the stability of the DFF, and the output of two balanced DFFs is more reliable. The entropy of output is fixed at 98.7%.展开更多
Physically unclonable crypto primitives have potential applications for anti-counterfeiting,identification,and authentication,which are clone proof and resistant to variously physical attack.Conventional physical uncl...Physically unclonable crypto primitives have potential applications for anti-counterfeiting,identification,and authentication,which are clone proof and resistant to variously physical attack.Conventional physical unclonable function(PUF)based on Si complementary metal-oxide-semiconductor(CMOS)technologies greatly suffers from entropy loss and bit instability due to noise sensitivity.Here we grow atomically thick MoS2 thin film and fabricate field-effect transistors(FETs).The inherently physical randomness of MoS2 transistors from materials growth and device fabrication process makes it appropriate for the application of PUF device.We perform electrical characterizations of MoS2 FETs,collect the data from 448 devices,and generate PUF keys by splitting drain current at specific levels to evaluate the response performance.Proper selection of splitting threshold enables to generate binary,ternary,and double binary keys.The generated PUF keys exhibit good randomness and uniqueness,providing a possibility for harvesting highly secured PUF devices with two-dimensional materials.展开更多
This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabri- cated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier,...This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabri- cated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical charac- teristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 ℃, and supply voltage variation from 1.7 to 1.9 V.展开更多
基金This work was supported by China Postdoctoral Science Foundation under Grant Nos.2020M681959 and 2020TQ0291in part by the national key R&D project under Grant No.2018YFB2100401in part by the National Key Research and Development Project No.2018YFB2100400.
文摘In the emerging Industrial Internet of Things(IIoT),authentication problems have become an urgent issue for massive resource-constrained devices because traditional costly security mechanisms are not suitable for them.The security protocol designed for resource-constrained systems should not only be secure but also efficient in terms of usage of energy,storage,and processing.Although recently many lightweight schemes have been proposed,to the best of our knowledge,they are unable to address the problem of privacy preservation with the resistance of Denial of Service(DoS)attacks in a practical way.In this paper,we propose a lightweight authentication protocol based on the Physically Unclonable Function(PUF)to overcome the limitations of existing schemes.The protocol provides an ingenious authentication and synchronization mechanism to solve the contradictions amount forward secrecy,DoS attacks,and resource-constrained.The performance analysis and comparison show that the proposed scheme can better improve the authentication security and efficiency for resource-constrained systems in IIoT.
文摘IoT devices rely on authentication mechanisms to render secure message exchange.During data transmission,scalability,data integrity,and processing time have been considered challenging aspects for a system constituted by IoT devices.The application of physical unclonable functions(PUFs)ensures secure data transmission among the internet of things(IoT)devices in a simplified network with an efficient time-stamped agreement.This paper proposes a secure,lightweight,cost-efficient reinforcement machine learning framework(SLCR-MLF)to achieve decentralization and security,thus enabling scalability,data integrity,and optimized processing time in IoT devices.PUF has been integrated into SLCR-MLF to improve the security of the cluster head node in the IoT platform during transmission by providing the authentication service for device-to-device communication.An IoT network gathers information of interest from multiple cluster members selected by the proposed framework.In addition,the software-defined secured(SDS)technique is integrated with SLCR-MLF to improve data integrity and optimize processing time in the IoT platform.Simulation analysis shows that the proposed framework outperforms conventional methods regarding the network’s lifetime,energy,secured data retrieval rate,and performance ratio.By enabling the proposed framework,number of residual nodes is reduced to 16%,energy consumption is reduced by up to 50%,almost 30%improvement in data retrieval rate,and network lifetime is improved by up to 1000 msec.
基金This work was supported in part by the National Science Foundation for Distinguished Young Scholars of China under Grant No. 61225012, the National Natural Science Foundation of China under Grant Nos. 61572123, 61501525, 61402162, 61232016, and U1405254, Hunan Province Science and Technology Project under Grant No. 2014RS4033, and the PAPD fund.
文摘Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.
基金Supported by the National Natural Science Foundation of China(41371402)the Fundamental Research Funds for the Central Universities(2015211020201)
文摘In order to reduce physical unclonable fixnction (PUF) response instability and imbalance caused by the metastability and the bias of arbiter, this paper uses an improved balanced D flip-plop (DFF) based on the unbalanced DFF to reduce the bias in response output and enhances the security of PUF by adopting two balanced DFFs in series. The experimental results show that two cascaded balanced DFFs improve the stability of the DFF, and the output of two balanced DFFs is more reliable. The entropy of output is fixed at 98.7%.
基金Research Grant Council of Hong Kong(PolyU 152016/17E)the Hong Kong Polytechnic University(G-SB79)J.-H.A.acknowledges the support from the National Research Foundation of Korea(NRF-2015R1A3A2066337).
文摘Physically unclonable crypto primitives have potential applications for anti-counterfeiting,identification,and authentication,which are clone proof and resistant to variously physical attack.Conventional physical unclonable function(PUF)based on Si complementary metal-oxide-semiconductor(CMOS)technologies greatly suffers from entropy loss and bit instability due to noise sensitivity.Here we grow atomically thick MoS2 thin film and fabricate field-effect transistors(FETs).The inherently physical randomness of MoS2 transistors from materials growth and device fabrication process makes it appropriate for the application of PUF device.We perform electrical characterizations of MoS2 FETs,collect the data from 448 devices,and generate PUF keys by splitting drain current at specific levels to evaluate the response performance.Proper selection of splitting threshold enables to generate binary,ternary,and double binary keys.The generated PUF keys exhibit good randomness and uniqueness,providing a possibility for harvesting highly secured PUF devices with two-dimensional materials.
基金Project supported by the National Natural Science Foundation of China(No.61376031)
文摘This paper describes a new silicon physical unclonable function (PUF) architecture that can be fabri- cated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier, comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical charac- teristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 μm CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from -40 to 100 ℃, and supply voltage variation from 1.7 to 1.9 V.