This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-idea...This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61106025)
文摘This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.
