This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-idea...This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.展开更多
设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流...设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。展开更多
随着电子技术迅猛发展,对模数转换器(ADC)在通信、图像处理等领域中的信号处理速度、精度的要求不断提升。流水线ADC作为高精度,高运行速度的模数处理模块,是影响流水线速度和精度的最关键因素。本文分析了3种传统的运放(套筒式、折叠...随着电子技术迅猛发展,对模数转换器(ADC)在通信、图像处理等领域中的信号处理速度、精度的要求不断提升。流水线ADC作为高精度,高运行速度的模数处理模块,是影响流水线速度和精度的最关键因素。本文分析了3种传统的运放(套筒式、折叠式以及密勒补偿式运放)的基本性能,并对这3种运放做了设计和仿真结果比较;分析对单端运放和全差分运放的性能区别,在设计和仿真结果上进行对比分析;设计应用于流水线ADC的运放,即能满足性能(8 m A,90db,900 M,60o)要求的增益自举运放。展开更多
A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stage...A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.展开更多
介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率...介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。展开更多
The article presents a new （1＋1）-bit/stage structure for pipelined analog-to-digital converters （ADC）. When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can s...The article presents a new （1＋1）-bit/stage structure for pipelined analog-to-digital converters （ADC）. When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators＇ decision levels. The ADC implemented in Semiconductor Manufactory International Corporation （SMIC） 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61106025)
文摘This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.
文摘设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。
文摘随着电子技术迅猛发展,对模数转换器(ADC)在通信、图像处理等领域中的信号处理速度、精度的要求不断提升。流水线ADC作为高精度,高运行速度的模数处理模块,是影响流水线速度和精度的最关键因素。本文分析了3种传统的运放(套筒式、折叠式以及密勒补偿式运放)的基本性能,并对这3种运放做了设计和仿真结果比较;分析对单端运放和全差分运放的性能区别,在设计和仿真结果上进行对比分析;设计应用于流水线ADC的运放,即能满足性能(8 m A,90db,900 M,60o)要求的增益自举运放。
文摘A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.
文摘设计了一种用于高速ADC中的全差分运算放大器。该运算放大器由主运放、4个辅助运放和一种改进型开关电容共模反馈电路组成,主运放采用折叠式共源共栅结构,并引入增益增强技术提高增益。采用SMIC 0.18μm,1.8 V工艺,在Cadence电路设计平台中利用Spectre仿真,结果表明:运放增益达到115 d B,单位增益带宽805 MHz,而功耗仅为10.5 m W,运放在8 ns的时间内可以达到0.01%的建立精度,可用于高速高精度流水线(Pipelined)ADC中。
文摘介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。
基金supported by the Project of Applied Materials (XA-AM-200506).
文摘The article presents a new （1＋1）-bit/stage structure for pipelined analog-to-digital converters （ADC）. When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators＇ decision levels. The ADC implemented in Semiconductor Manufactory International Corporation （SMIC） 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.
