针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifier...A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.展开更多
设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态...设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.展开更多
A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stage...A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.展开更多
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
文摘A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.
文摘设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.
文摘A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.
