A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sa...A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the ...Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, w...A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.展开更多
A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the prec...A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.展开更多
The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator ...The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.展开更多
为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提...为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。展开更多
设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流...设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。展开更多
Effectiveness evaluation of the joint operation system is an important basis for the demonstration and development of weapon equipment.With the consideration that existing models of system effectiveness evaluation sel...Effectiveness evaluation of the joint operation system is an important basis for the demonstration and development of weapon equipment.With the consideration that existing models of system effectiveness evaluation seldom describe the structural relationship among equipment clearly as well as reflect the dynamic,the analog-to-digital converter-graphical evaluation and review technique(ADC-GERT)network parameter estimation model is proposed based on the ADC model and the joint operation system structure.Firstly,analysis of the joint operation system structure and operation process is conducted to build the GERT network,where equipment subsystems are nodes and activities are directed arches.Then the mission effectiveness of equipment subsystems is calculated by the ADC model.The probability transfer parameters are modified by the mission effectiveness of equipment subsystems based on the Bayesian theorem,with the ADC-GERT network parameter estimation model constructed.Finally,a case study is used to validate the efficiency and dynamic of the ADC-GERT network parameter estimation model.展开更多
基金The National Science Fund for Creative Re-search Groups( Grant No 60521002 )Shanghai Natural Science Foundation (GrantNo 037062022)
文摘A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
文摘Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
基金Supported by the Doctoral Program Foundation of Institutions of Higher Education of China (No.20120111120008)State Key Lab of ASIC & System(Fudan University) (No. 11KF001)Special Fund for Doctoral Program (Hefei University of Technology) (No.2011HGBZ0953)
文摘A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
基金supported by National Natural Science Foundation of China under grant No.61704161Key Project of Natural Science of Anhui Provincial Department of Education under grant No.KJ2017A396
文摘A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.
基金Supported by the National Natural Science Foundation of China (No. 60072004)
文摘The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.
文摘为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。
文摘设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
基金supported by the National Natural Science Foundation of China(72071111,71801127,71671091)the NSFC and the UK Royal Society joint project(71811530338)+2 种基金the Special Postdoctoral Fund of China(2019TQ0150)the Fundamental Research Funds for the Central Universities of China(NC2019003)the Intelligence Introduction Base of the Ministry of Science and Technology(G20190010178)。
文摘Effectiveness evaluation of the joint operation system is an important basis for the demonstration and development of weapon equipment.With the consideration that existing models of system effectiveness evaluation seldom describe the structural relationship among equipment clearly as well as reflect the dynamic,the analog-to-digital converter-graphical evaluation and review technique(ADC-GERT)network parameter estimation model is proposed based on the ADC model and the joint operation system structure.Firstly,analysis of the joint operation system structure and operation process is conducted to build the GERT network,where equipment subsystems are nodes and activities are directed arches.Then the mission effectiveness of equipment subsystems is calculated by the ADC model.The probability transfer parameters are modified by the mission effectiveness of equipment subsystems based on the Bayesian theorem,with the ADC-GERT network parameter estimation model constructed.Finally,a case study is used to validate the efficiency and dynamic of the ADC-GERT network parameter estimation model.
