A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ult...A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.展开更多
Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photol...Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.展开更多
文摘A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.
文摘Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.
