Physical mechanism of secondary-electron emission in Si wafers

CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.

Wafer Defect Map Pattern Recognition Based on Improved ResNet

The defect detection of wafers is an important part of semiconductor manufacturing.The wafer defect map formed from the defects can be used to trace back the problems in the production process and make improvements in the yield of wafer manufacturing.Therefore,for the pattern recognition of wafer defects,this paper uses an improved ResNet convolutional neural network for automatic pattern recognition of seven common wafer defects.On the basis of the original ResNet,the squeeze-and-excitation(SE)attention mechanism is embedded into the network,through which the feature extraction ability of the network can be improved,key features can be found,and useless features can be suppressed.In addition,the residual structure is improved,and the depth separable convolution is added to replace the traditional convolution to reduce the computational and parametric quantities of the network.In addition,the network structure is improved and the activation function is changed.Comprehensive experiments show that the precision of the improved ResNet in this paper reaches 98.5%,while the number of parameters is greatly reduced compared with the original model,and has well results compared with the common convolutional neural network.Comprehensively,the method in this paper can be very good for pattern recognition of common wafer defect types,and has certain application value.

Nanogrinding of SiC wafers with high flatness and low subsurface damage

Nanogrinding of SiC wafers with high flatness and low subsurface damage was proposed and nanogrinding experiments were carried out on an ultra precision grinding machine with fine diamond wheels. Experimental results show that nanogrinding can produce flatness less than 1.0μm and a surface roughness Ra of 0.42nm. It is found that nanogrinding is capable of producing much flatter SiC wafers with a lower damage than double side lapping and mechanical polishing in much less time and it can replace double side lapping and mechanical polishing and reduce the removal amount of chemical mechanical polishing.

An Improved Angle Polishing Method for Measuring Subsurface Damage in Silicon Wafers

We present an improved angle polishing method in which the end of the cover slice near the glue layer is beveled into a thin,defect-free wedge,the straight edge of which is used as the datum for measuring the depth of subsurface damage. The bevel angle can be calculated from the interference fringes formed in the wedge. The minimum depth of the subsurface damage that can be measured by this method is a few hundred nanometers. Our results show that the method is straightforward, accurate, and convenient.

A Diamond Electrochemical Cleaning Technique for Organic Contaminants on Silicon Wafer Surfaces

Peroxodiphosphate anion （a powerful oxidant） can be formed in a special water-based cleaning agent through an electrochemical reaction on boron-doped diamond electrodes. This electrochemical reaction was applied during the oxidation,decomposition, and removal of organic contaminations on a silicon wafer surface, and it was used as the first step in the diamond electrochemical cleaning technique （DECT）. The cleaning effects of DECT were compared with the RCA cleaning technique, including the silicon surface chemical composition that was observed with X-ray photoelectron spectroscopy and the morphology observed with atomic force microscopy. The measurement results show that the silicon surface cleaned by DECT has slightly less organic residue and lower micro-roughness,so the new technique is more effective than the RCA cleaning technique.

Drop failure modes of Sn-3.0Ag-0.5Cu solder joints in wafer level chip scale package

To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.

Transfer of Thin Epitaxial Silicon Films by Wafer Bonding and Splitting of Double Layered Porous Silicon for SOI Fabrication

A double layered porous silicon with different porosity is formed on a heavy doped p type Si(111) substrate by changing current density during the anodizing.Then a high quality epitaxial mono crystalline silicon film is grown on the porous silicon using an ultra high vacuum electron beam evaporator.This wafer is bonded with other silicon wafer with a thermal oxide layer at room temperature.The bonded pairs are split along the porous silicon layer during subsequent thermal annealing.Thus the epitaxial Si film is transferred to the oxidized wafer to form a silicon on insulator structure.SEM,XTEM,spreading resistance probe and Hall measurement show that the SOI structure has good structural and electrical quality.

腕关节镜下Wafer术治疗尺骨撞击综合征26例围手术期护理体会

目的探索腕关节镜下尺骨头部分磨除术(Wafe术)治疗尺骨撞击综合征的围手术期护理。方法在26例尺骨撞击综合征患者行腕关节镜下Wafer术治疗期间,实施术前心理疏导、完善准备、术后并发症的预防与观察等护理措施。结果 26例患者均顺利完成手术,术后分别出现1例引流管积血阻塞和1例尺神经浅支损伤,均经对症处理后痊愈,未发生其他严重并发症。术后2个月采用改良Mayo评分评定腕关节功能,本组优良率100.00%(26/26)。术后3个月肌力恢复均至健侧80%以上。未发生腕部疼痛及严重腕关节活动受限等后遗症。结论对尺骨撞击综合征患者实施腕关节镜下Wafer术治疗期间,全面而细致行围术期护理,有助于减少术后并发症,提升手术效果和促进腕关节功能的恢复。

Effect of Rapid Thermal Annealing Ambient on Gettering Efficiency and Surface Microstructure in 300mm CZ Silicon Wafers

The effect of rapid thermal annealing （RTA） ambient on denuded zone and oxygen precipitates in Czochralski （CZ） silicon wafers is studied in this paper. N2 and a N2/NH3 mixture are used as RTA ambient. It is demonstrated that a high density of oxygen precipitates and thin denuded zone are obtained in N2/NH3 ambient,while a relatively lower density of oxygen precipitates and thicker denuded zone are observed in N2 ambient. As the RTA duration times increased, the oxygen precipitate density increased and the denuded zone depth decreased. X-ray photoelectron spectroscopy （XPS） data and atomic force microscope （AFM） results show that there RTA process,which can explain the different effect of RTA was a surface nitriding reaction during the N2/NH3 ambient ambient.

STUDIES OF SURFACE GRINDING TEMPERATURE AFFECTED BY DIFFERENT GRINDING WAYS OF SILICON WAFER

The surface grinding temperature of the silicon wafer ground by diamond wheels is studied.Rudimentally,the properties of the surface grinding temperature generated by two grinding methods,ground by straight and cup wheels respectively,are analyzed.In addition,considering the effects of grain size and grinding depth on surface grinding temperature during these two grinding processes,significant results and conclusions are obtained from experimental research.

Microstructure studies of the grinding damage in monocrystalline silicon wafers

The depth and nature of the subsurface damage in a silicon wafer will limit the performance of IC components. Damage microstructures of the silicon wafers ground by the #325, #600, and #2000 grinding wheels was analyzed. The results show that many microcracks, fractures, and dislocation rosettes appear in the surface and subsurface of the wafer ground by the #325 grinding wheel. No obvious microstructure change exists. The amorphous layer with a thickness of about 100 nm, microcracks, high density dislocations, and polycrystalline silicon are observed in the subsurface of the wafer ground by the #600 grinding wheel. For the wafer ground by the #2000 grinding wheel, an amorphous layer of about 30 nm thickness, a polycrystalline silicon layer, a few dislocations, and an elastic deformation layer exist. In general, with the decrease in grit size, the material removal mode changes from micro-fracture mode to ductile mode gradually.

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.

Damage mechanisms during lapping and mechanical polishing CdZnTe wafers

CdZnTe wafers were machined by lapping and mechanical polishing processes,and their surface and subsurface damages were investigated.The surface damages are mainly induced by three-body abrasive wear and embedded abrasive wear during lapping process.A new damage type,which is induced by the indentation of embedded abrasives,is found in the subsurface.When a floss pad is used to replace the lapping plate during machining,the surface damage is mainly induced by two-body abrasive and three-body abrasive wear,and the effect of embedded abrasives on the surface is greatly weakened.Moreover,this new damage type nearly disappears on the subsurface.

Residual stress analysis on silicon wafer surface layers induced by ultraprecision grinding

Grinding residual stresses of silicon wafers affect the performance of IC circuits. Based on the wafer rotation ultra-precision grinding ma-chine, the residual stress distribution along grinding marks and ground surface layer depth of the ground wafers are investigated using Raman microspectroscopy. The results show that the ground wafer surfaces mainly present compressive stress. The vicinity of pile-ups between two grinding marks presents higher a compressive stress. The stress value of the rough ground wafer is the least because the material is removed by the brittle fracture mode. The stress of the semi-fine ground wafer is the largest because the wafer surface presents stronger phase trans-formations and elastic-plastic deformation. The stress of the fine ground wafer is between the above two. The strained layer depths for the rough, semi-fine, and fine ground wafers are about 7.6 m, 2.6 m, and 1.1 m, respectively. The main reasons for generation of residual stresses are phase transformations and elastic-plastic deformation.

Coaxial Twin-shaft Magnetic Fluid Seals Applied in Vacuum Wafer-Handling Robot

Compared with traditional mechanical seals,magnetic fluid seals have unique characters of high airtightness,minimal friction torque requirements,pollution-free and long life-span,widely used in vacuum robots.With the rapid development of Integrate Circuit（IC）,there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment.The parameters of magnetic fluid seals structure is very important in the vacuum robot design.This paper gives a magnetic fluid seal device for the robot.Firstly,the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics,which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal.Secondly,the magnetic analysis model of twin-shaft magnetic fluid seals structure is established.By analyzing the magnetic field distribution of dual magnetic fluid seal,the optimal value ranges of important parameters,including parameters of the permanent magnetic ring,the magnetic pole tooth,the outer shaft,the outer shaft sleeve and the axial relative position of two permanent magnetic rings,which affect the seal differential pressure,are obtained.A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built.Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min,the maximum burst pressure is about 0.24 MPa.Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot.The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

Modeling and Validation of Indentation Depth of Abrasive Grain into Lithium Niobate Wafer by Fixed-Abrasive Lapping

The prediction of indentation depth of abrasive grain in hydrophilic fixed-abrasive(FA)lapping is crucial for controlling material removal rate and surface quality of the work-piece being machined.By applying the theory of contact mechanics,a theoretical model of the indentation depth of abrasive grain was developed and the relationships between indentation depth and properties of contact pairs and abrasive back-off were studied.Also,the average surface roughness(Ra)of lapped wafer was approximately calculated according to the obtained indentation depth.To verify the rationality of the proposed model,a series of lapping experiments on lithium niobate(LN)wafers were carried out,whose average surface roughness Ra was measured by atomic force microscope(AFM).The experimental results were coincided with the theoretical predictions,verifying the rationality of the proposed model.It is concluded that the indentation depth of the fixed abrasive was primarily affected by the applied load,wafer micro hardness and pad Young′s modulus and so on.Moreover,the larger the applied load,the more significant the back-off of the abrasive grain.The model established in this paper is helpful to the design of FA pad and its machining parameters,and the prediction of Ra as well.

Scheduling Dual-Arm Cluster Tools With Multiple Wafer Types and Residency Time Constraints

Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual customization, which poses a huge challenge to the scheduling of cluster tools with single-wafer-type fabrication. Concurrent processing multiple wafer types in cluster tools, as a novel production pattern, has drawn increasing attention from industry to academia, whereas the corresponding research remains insufficient. This paper investigates the scheduling problems of dual-arm cluster tools with multiple wafer types and residency time constraints. To pursue an easy-to-implement cyclic operation under diverse flow patterns,we develop a novel robot activity strategy called multiplex swap sequence. In the light of the virtual module technology, the workloads that stem from bottleneck process steps and asymmetrical process configuration are balanced satisfactorily. Moreover, several sufficient and necessary conditions with closed-form expressions are obtained for checking the system's schedulability. Finally, efficient algorithms with polynomial complexity are developed to find the periodic scheduling, and its practicability and availability are demonstrated by the offered illustrative examples.

110 GHz可溯源的On-wafer GaAs基Multi-TRL校准标准件研制

设计制作了用于1~110GHzOn-wafer散射参数测试系统自校准的GaAs基Multi-TRL校准标准件。主要验证了Multi-TRL校准标准件设计的正确性;经过与国外计量标准及商用校准件比对,还验证了在频率范围1GHz^110GHz,用于Multi-TRL校准的校准标准件的准确性。

SHAPE BIFURCATION OF AN ELASTIC WAFER DUE TO SURFACE STRESS

A geometrically nonlinear analysis was proposed for the deformation of a free standing elastically isotropic wafer caused by the surface stress change on one surface. The link between the curvature and the change in surface stress was obtained analytically from energetic consideration. In contrast to the existing linear analysis, a remarkable consequence is that, when the wafer is very thin or the surface stress difference between the two major surfaces is large enough, the shape of the wafer will bifurcate.

Bottleneck Identification and Prediction of Wafer Fabrication Systems in Transient States

According to theory of constraints( TOCs), the performance of a complex manufacturing system,such as a wafer fabrication system,is mainly determined by its bottleneck machine.A method of the identification and prediction of the bottleneck machine was proposed in transient states of a system. Firstly,the bottleneck index was formulated based on the workloads and the variability in wafer fabrication systems. Secondly, main factors causing the variability and their influences on the bottleneck machine in transient states of the system were analyzed and discussed. An effective bottleneck identification and prediction model was presented,which incorporated the variability and queuing theory,and took machine breakdowns and setups into considerations.Finally,the proposed bottleneck prediction method was verified by simulation experiments. Results indicate that the proposed bottleneck prediction method is feasible and effective.