Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends

In this paper, we describe resourceefficient hardware architectures for softwaredefined radio （SDR） frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array （FPGA） based architectures in an Mpath polyphase filter bank with modified Npath polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A nonmaximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the Mdataload ＇ s time period. We present a loadprocess architecture （LPA） and a runtime architecture （RA） （based on serial polyphase structure） which have different scheduling. In LPA, Nsubfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, Msubfilters processes are efficiently scheduled within Ndataload time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, underdecimated, overdecimated, and combined upand downsampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resourceoptimized SDR frontends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are prestored in LUTs.

Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

This paper presents efficient processing engines for software-defined radio （SDR） front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filterbank （where the number of data loads is not equal to the number of M subfilters） processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resamp/ing in SDR front-ends. These modes are （i） maximally decimated, （ii） Under-decimated, （iii） over-decimated, and combined up- and down-sampling with （iv） single stride length, and （v） multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

Symbol Synchronization of Single-Carrier Signal with Ultra-Low Oversampling Rate Based on Polyphase Filter

An efficient single-carrier symbol synchronization method is proposed in this paper,which can work under a very low oversampling rate.This method is based on the frequency aliasing squared timing recovery assisted by pilot symbols and time domain filter.With frequency aliasing squared timing recovery with pilots,it is accessible to estimate timing error under oversampling rate less than 2.The time domain filter simultaneously performs matched-filtering and arbitrary interpolation.Because of pilot assisting,timing error estimation can be free from alias and self noise,so our method has good performance.Compared with traditional time-domain methods requiring oversampling rate above 2,this method can be adapted to any rational oversampling rate including less than 2.Moreover,compared with symbol synchronization in frequency domain which can operate under low oversampling rate,our method saves the complicated operation of conversion between time domain and frequency domain.By low oversampling rate and resource saving filter,this method is suitable for ultra-high-speed communication systems under resource-restricted hardware.The paper carries on the simulation and realization under 64QAM system.The simulation result shows that the loss is very low(less than 0.5 dB),and the real-time implementation on field programmable gate array(FPGA)also works fine.

High-Speed Parallel Matched Filter Designing and FPGA Implementation

Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper,a parallel finite-impulse response (FIR) filter structure based on polyphase filter-ing is used to achieve high-speed matched filter in quadrature phase-shift keying (QPSK) demodulation up to 800 Mb·s-1. First,a window function is employed of to obtain impulse response of matched filter. Second,the high-speed parallel FIR structure is presented based on polyphase filtering. Then,the filter with EP2S180F1020 on the Quartus II 7.2 platform is achieved. The final results show that the design is correct and can implement high-speed matched filtering,wherein the equivalent frequency of which is up to 2 037 MHz. In addition,this scheme is easy to real-ize,which brings great value to the application of this filter in high-speed matched filters design in demodulation systems.

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.