A physical surface-potential-based drain current model for polysilicon thin-film transistors

A physical drain current model of polysilicon thin-film transistors based on the charge-sheet model, the density of trap states and surface potential is proposed.The model uses non-iterative calculations,which are single-piece and valid in all operation regions above flat-band voltage.The distribution of the trap states,including both Gaussian deep-level states and exponential band-tail states,is also taken into account,and parameter extraction of trap state distribution is developed by the optoelectronic modulation spectroscopy measurement method. Comparisons with the available experimental data are accomplished,and good agreements are obtained.

Heterojunction-engineered carrier transport in elevated-metal metal-oxide thin-film transistors

This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.

Implementation of sub-100 nm vertical channel-all-around(CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In-Ga-Zn-O(IGZO) channel based thin-film transistors(TFT), which exhibit high on-off current ratio and relatively high mobility, has been widely researched due to its back end of line(BEOL)-compatible potential for the next generation dynamic random access memory(DRAM) application. In this work, thermal atomic layer deposition(TALD) indium gallium zinc oxide(IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition(ALD) process. In addition, thin-film transistors(TFTs) with vertical channel-all-around(CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Indium-gallium-zinc-oxide thin-film transistors:Materials,devices,and applications

Since the invention of amorphous indium-gallium-zinc-oxide(IGZO)based thin-film transistors(TFTs)by Hideo Hosono in 2004,investigations on the topic of IGZO TFTs have been rapidly expanded thanks to their high electrical performance,large-area uniformity,and low processing temperature.This article reviews the recent progress and major trends in the field of IGZO-based TFTs.After a brief introduction of the history of IGZO and the main advantages of IGZO-based TFTs,an overview of IGZO materials and IGZO-based TFTs is given.In this part,IGZO material electron travelling orbitals and deposition methods are introduced,and the specific device structures and electrical performance are also presented.Afterwards,the recent advances of IGZO-based TFT applications are summarized,including flat panel display drivers,novel sensors,and emerging neuromorphic systems.In particular,the realization of flexible electronic systems is discussed.The last part of this review consists of the conclusions and gives an outlook over the field with a prediction for the future.

High-Performance Photo-Modulated Thin-Film Transistor Based on Quantum dots/Reduced Graphene Oxide Fragment-Decorated ZnO Nanowires

In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se quantum dots and reduced graphene oxide(RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 AW^(-1) and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.

Modeling of an Internal Stress and Strain Distribution of an Inverted Staggered Thin-Film Transistor Based on Two-Dimensional Mass-Spring-Damper Structure

Equipped with a two-dimensional topological structure,a group of masses,springs and dampers can be demonstrated to model the internal dynamics of a thin-film transistor(TFT).In this paper,the two-dimensional Mass-Spring-Damper(MSD)representation of an inverted staggered TFT is proposed to explore the TFT’s internal stress/strain distributions,and the stress-induced effects on TFT’s electrical characteristics.The 2DMSD model is composed of a finite but massive number of interconnected cellular units.The parameters,such as mass,stiffness,and damping ratios,of each cellular unit are approximated from constitutive equations of the compositematerials,while the electrical properties of the inverted staggered TFT are characterized by utilizing an electro-mechanical coupling relation derived from the quantum mechanics.TFTs are often used in biomedical sensors/transducers attached to human skins,and,for the purpose of simulation and validation,the boundary conditions on the interface between the TFT and the human skin were modeled as a spatially distributed sinusoidal excitation with a frequency of 50 Hz,assuming the TFT thickness is more than tens of microns.The fidelity of the 2D MSD structure in the modeling of an inverted staggered TFT is verified by comparing its simulated total displacement fieldwith that of a finite element analysis(FEA)model.The advantages of the MSD model include a dramatic reduction in memory use by up to 60%and faster computation times that are up to 80%lower.More importantly,the MSD model is better suited than FEA to many problems in accurate tissue modeling for medical applications,for which FEA is becoming a bottleneck.This work develops a novel modeling approach,which can be extended to other types of flexible thin film transistors.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Al_(2)O_(3)/HfO_(2) Nanolaminate Dielectric Boosting IGZO-Based Flexible Thin-Film Transistors

Flexible thin-film transistors(TFTs)have attracted wide interest in the development of flexible and wearable displays or sensors.However,the conventional high processing temperatures hinder the preparation of stable and reliable dielectric materials on flexible substrates.Here,we develop a stable laminated Al_(2)O_(3)/HfO_(2) insulator by atomic layer deposition at a relatively lower temperature of 150℃.A sputtered amorphous indium-gallium-zinc oxide(IGZO)with the stoichiometry of In_(0.37)Ga_(0.20)Zn_(0.18)O_(0.25) is used as the active channel material.The flexible TFTs with bottom-gate top-contacted configuration are further fabricated on a flexible polyimide substrate with the Al_(2)O_(3)/HfO_(2) nanolaminates.Benefited from the unique structural and compositional configuration in the nanolaminates consisting of amorphous Al_(2)O_(3),crystallized HfO_(2),and the aluminate Al-Hf-O phase,the as-prepared TFTs present the carrier mobilities of 9.7 cm^(2) V^(−1) s^(−1),ON/OFF ratio of-1.3×10^(6),subthreshold voltage of 0.1 V,saturated current up to 0.83 mA,and subthreshold swing of 0.256 V dec^(−1),signifying a high-performance flexible TFT,which simultaneously able to withstand the bending radius of 40 mm.The TFTs with nanolaminate insulator possess satisfactory humidity stability and hysteresis behavior in a relative humidity of 60-70%,a temperature of 25-30℃ environment.The yield of IGZO-based TFTs with the nanolaminate insulator reaches 95%.

Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

Flexible and transparent electronics enters into a new era of electronic technologies.Ubiquitous applications involve wearable electronics,biosensors,flexible transparent displays,radio-frequency identifications（RFIDs）,etc.Zinc oxide（ZnO） and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices,owing to their high electrical performances,together with low processing temperatures and good optical transparencies.In this paper,we review recent advances in flexible and transparent thin-film transistors（TFTs） based on ZnO and relevant materials.After a brief introduction,the main progress of the preparation of each component（substrate,electrodes,channel and dielectrics） is summarized and discussed.Then,the effect of mechanical bending on electrical performance is highlighted.Finally,we suggest the challenges and opportunities in future investigations.

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.

A systematic study of light dependency of persistentphotoconductivity in a-InGaZnO thin-film transistors

Persistent photoconductivity(PPC)effect and its light-intensity dependence of both enhancement and depletion(E-/D-)mode amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs)are systematically investigated.Density of oxygen vacancy(V O)defects of E-mode TFTs is relatively small,in which formation of the photo-induced metastable defects is thermally activated,and the activation energy(E a)decreases continuously with increasing light-intensity.Density of V O defects of D-mode TFTs is much larger,in which the formation of photo-induced metastable defects is found to be spontaneous instead of thermally activated.Furthermore,for the first time it is found that a threshold dose of light-exposure is required to form fully developed photo-induced metastable defects.Under low light-exposure below the threshold,only a low PPC barrier is formed and the PPC recovery is fast.With increasing the light-exposure to the threshold,the lattice relaxation of metal cations adjacent to the doubly ionized oxygen vacancies(V O^2+)is fully developed,and the PPC barrier increases to∼0.25 eV,which remains basically unchanged under higher light-exposure.Based on the density of V O defects in the channel and the condition of light illumination,a unified model of formation of photo-induced metastable defects in a-IGZO TFTs is proposed to explain the experimental observations.

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress(NBS)reliability of n-type polycrystalline silicon(poly-Si)thin-film transistors(TFTs)with a distinct defective grain boundary(GB)in the channel is investigated.Results show that conventional NBS degradation with negative shift of the transfer curves is absent.The on-state current is decreased,but the subthreshold characteristics are not affected.The gate bias dependence of the drain leakage current at V_(ds)of 5.0 V is suppressed,whereas the drain leakage current at V_(ds)of 0.1 V exhibits obvious gate bias dependence.As confirmed via TCAD simulation,the corresponding mechanisms are proposed to be trap state generation in the GB region,positive-charge local formation in the gate oxide near the source and drain,and trap state introduction in the gate oxide.

Degradation mechanisms for a-InGaZnO thin-film transistors functioning under simultaneous DC gate and drain biases

Degradation of a-InGaZnO thin-film transistors working under simultaneous DC gate and drain bias stress is investigated,and the corresponding degradation mechanism is proposed and verified.The maximum degradation occurs under the bias stress condition that makes the electric field and electron concentration relatively high at the same time.Trapping of hot electrons in the etching-stop layer under the extended drain electrode is proven to be the underlying mechanism.The observed degradation phenomena,including distortion in the transfer curve on a logarithmic scale and two-slope dependence on gate bias on a linear scale,current crowding in the output curve,and smaller degradation in transfer curves measured under large drain bias,can all be well explained with the proposed degradation mechanism.

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress(NBS)is observed for amorphous InGaZnO(a-IGZO)thin-film transistors(TFTs),which can recover in a short time.After comparing with the degradation phenomena under negative bias illumination stress(NBIS),positive bias stress(PBS),and positive bias illumination stress(PBIS),degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies(V_(o)^(+))in addition to the commonly reported doubly charged oxygen vacancies(V_(o)^(2+)).Furthermore,the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of V_(o)^(+)under positive gate bias.The proposed degradation mechanisms are verified by TCAD simulation.

Electrical properties of zinc-oxide-based thin-film transistors using strontium-oxide-doped semiconductors

Strontium-zinc-oxide（SrZnO） films forming the semiconductor layers of thin-film transistors（TFTs） are deposited by using ion-assisted electron beam evaporation. Using strontium-oxide-doped semiconductors, the off-state current can be dramatically reduced by three orders of magnitude. This dramatic improvement is attributed to the incorporation of strontium, which suppresses carrier generation, thereby improving the TFT. Additionally, the presence of strontium inhibits the formation of zinc oxide（ZnO） with the hexagonal wurtzite phase and permits the formation of an unusual phase of ZnO, thus significantly changing the surface morphology of ZnO and effectively reducing the trap density of the channel.

Performance enhancement of solution-processed InZnO thin-film transistors by Al doping and surface passivation

Solution-processed oxide semiconductors have been considered as a potential alternative to vacuum-based ones in printable electronics.However,despite spincoated InZnO(IZO)thin-film transistors(TFTs)have shown a relatively high mobil-ity,the lack of carrier suppressor and the high sensitivity to oxygen and water molecules in ambient air make them potentially suffer issues of poor stability.In this work,Al is used as the third cation doping element to study the effects on the electrical,optoelectronic,and physical properties of IZO TFTs.A hydrophobic self-assembled monolayer called octadecyltrimethoxysilane is introduced as the surface passivation layer,aiming to reduce the effects from air and understand the importance of top surface conditions in solution-processed,ultra-thin oxide TFTs.Owing to the reduced trap states within the film and at the top surface enabled by the doping and passivation,the optimized TFTs show an increased current on/off ratio,a reduced drain current hysteresis,and a significantly enhanced bias stress stability,compared with the untreated ones.By combining with high-capacitance AlO_(x),TFTs with a low operating voltage of 1.5 V,a current on/off ratio of>10^(4) and a mobility of 4.6 cm^(2)/(V·s)are demonstrated,suggesting the promising features for future low-cost,low-power electronics.

Research on the electrical characteristics of an organic thin-film field-effect transistor based on alternating-current resistance

In this article, an organic thin-film field-effect transistor （OTFFET） with top-gate and bottom-contact geometry based on pentacene as the active layer is fabricated. The experimental data of the I-V are obtained from the OTFFET device. The alternating-current （AC） resistance value of the OTFFET device is calculated using the derivation method from the experimental data, and the AC resistance trend curves of the OTFFET device are obtained with the region fitting method. We analyse the characteristics of the OTFFET device with an AC resistance trend curve. To discover whether it has a high resistance, it is proposed to judge the region of the source/drain voltage （VDs） less than the transition voltage, thereby determining whether the contact between the metal electrode and the organic semiconductor layer of the OTFFET device is Ohmic or non-Ohmic. The theoretical analysis shows that the field-effect mobility and the AC resistance are in reverse proportion. Therefore, we point out that reducing AC resistance is necessary if field-effect mobility is to be improved.