Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in material...Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in materials, device performance, OFETs based circuits in recent years. In this article we introduce the advances in organic semiconductor materials, OFETs based integrating techniques, and in particular highlight the recent progress. Finally, the prospects and problems of OFETs are discussed.展开更多
The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital de...The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.展开更多
SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同...SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。展开更多
基金Supported by the National Basic Research Program of China ("973" Project) (Grant Nos. 2006CB806204, 2009CB939703)the National Natural Science Foundation of China (Grant Nos. 90607022, 60676001, 60676008, 60825403)
文摘Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in materials, device performance, OFETs based circuits in recent years. In this article we introduce the advances in organic semiconductor materials, OFETs based integrating techniques, and in particular highlight the recent progress. Finally, the prospects and problems of OFETs are discussed.
文摘The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
