Combined Novel Gate Level Model and Critical Primary Input Sharing for Genetic Algorithm Based Maximum Power Supply Noise Estimation

A gate level maximum power supply noise （PSN） model is defined that captures both IR drop and di/dt noise effects. Experimental results show that this model improves PSN estimation by 5.3% on average and reduces computation time by 10.7% compared with previous methods. Furthermore,a primary input critical factor model that captures the extent of primary inputs＇ PSN contribution is formulated. Based on these models,a novel niche genetic algorithm is proposed to estimate PSN more effectively. Compared with general genetic algorithms, this novel method can achieve up to 19.0% improvement on PSN estimation with a much higher convergence speed.

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

11.2 W/mm power density AlGaN/GaN high electron-mobility transistors on a GaN substrate

In this letter,high power density AlGaN/GaN high electron-mobility transistors(HEMTs)on a freestanding GaN substrate are reported.An asymmetricΓ-shaped 500-nm gate with a field plate of 650 nm is introduced to improve microwave power performance.The breakdown voltage(BV)is increased to more than 200 V for the fabricated device with gate-to-source and gate-to-drain distances of 1.08 and 2.92μm.A record continuous-wave power density of 11.2 W/mm@10 GHz is realized with a drain bias of 70 V.The maximum oscillation frequency(f_(max))and unity current gain cut-off frequency(f_(t))of the AlGaN/GaN HEMTs exceed 30 and 20 GHz,respectively.The results demonstrate the potential of AlGaN/GaN HEMTs on freestanding GaN substrates for microwave power applications.

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array （FPGA） electronic design automation （EDA） tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.

Design of Low Power Transmission Gate Based 9T SRAM Cell

Considerable research has considered the design of low-power and high-speed devices.Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices.Embedded static random-access memory(SRAM)units are necessary components in fast mobile computing.Traditional SRAM cells are more energyconsuming and with lower performances.The major constraints in SRAM cells are their reliability and low power.The objectives of the proposed method are to provide a high read stability,low energy consumption,and better writing abilities.A transmission gate-based multi-threshold single-ended Schmitt trigger(ST)9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed.Herein,an ST inverter with a single bit-line design is used to attain the high read stability.A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter.The multithreshold complementary metal oxide semiconductor(MTCMOS)technique is adopted to reduce the leakage power in the proposed single-ended TGST 9T SRAM cell.The proposed system uses a combination of standard and ST inverters,which results in a large read stability.Compared with the previous ST 9T,ST 11T,11T,10T,and 7T SRAM cells,the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%,42.09%,31.60%,12.54%,and 31.60%less energy for read operations and 73.59%,93.95%,92.76%,89.23%,and 85.78%less energy for write operations,respectively.

Fast Rail Defect Inspection Based on Half-Cycle Power Demodulation Method and FPGA Implementation

In this paper,a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed.For this method,the power characters of de-tection signal which represent the degree of rail track can be calculated using only half-cycle detec-tion signal because of the symmetry characteristic of detected sine signal and reference signal.The theoretical analysis,simulation results and experiment results show that the demodulation preci-sion of proposed method is almost equal to fast Fourier transform(FFT)demodulation method and orthogonal demodulation method,but has high demodulation efficiency and less FPGA resources cost.A high-speed experiment system based on three coils structured sensor is built for rail inspec-tion experiment at a moving speed of 200 km/h.The experiment results show that proposed meth-od is more effective for rail inspection and the time resolution of proposed method is double of clas-sic method that based on FFT and orthogonal.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Impacts of NBTI/PBTI on power gated SRAM

A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

Pressure Tolerant Power Electronics： IGBT Gate Driver for Operation in High Pressure Hydrostatic Environment

Abstract： This paper presents results from an on-going research project on pressure tolerant power electronics at SINTEF Energy Research, Norway. The driving force for this research is to enable power electronic components to operate in pressurized dielectric environment. The intended application is the converters for operation down to 3,000 meters ocean depth, primarily for subsea oil and gas processing. The paper focuses on the needed modifications to a general purpose gate driver for IGBT （insulated gate bipolar transistors） that will give pressure tolerance. Adaptations and modifications of the individual driver components are presented.The results from preliminary testing are promising, which shows that the considered adaptations give feasible solutions.

Price prediction of power transformer materials based on CEEMD and GRU

The rapid growth of the Chinese economy has fueled the expansion of power grids.Power transformers are key equipment in power grid projects,and their price changes have a significant impact on cost control.However,the prices of power transformer materials manifest as nonsmooth and nonlinear sequences.Hence,estimating the acquisition costs of power grid projects is difficult,hindering the normal operation of power engineering construction.To more accurately predict the price of power transformer materials,this study proposes a method based on complementary ensemble empirical mode decomposition(CEEMD)and gated recurrent unit(GRU)network.First,the CEEMD decomposed the price series into multiple intrinsic mode functions(IMFs).Multiple IMFs were clustered to obtain several aggregated sequences based on the sample entropy of each IMF.Then,an empirical wavelet transform(EWT)was applied to the aggregation sequence with a large sample entropy,and the multiple subsequences obtained from the decomposition were predicted by the GRU model.The GRU model was used to directly predict the aggregation sequences with a small sample entropy.In this study,we used authentic historical pricing data for power transformer materials to validate the proposed approach.The empirical findings demonstrated the efficacy of our method across both datasets,with mean absolute percentage errors(MAPEs)of less than 1%and 3%.This approach holds a significant reference value for future research in the field of power transformer material price prediction.

Design and Verification of FPGA-Based Applications in Nuclear Power Plants

Nuclear industries have faced the unfavorable circumstance such as components obsolescence and aging of instrumentation and control system, therefore, nuclear society is striving to resolve this issue fundamentally. Various studies have been conducted to address components obsolescence of instrumentation and control system. Intuitively FPGA （field programmable gate arrays） technology is replacing the high level of micro-processor type equipped with various software and hardware which causes acceleration of the aging and obsolescence in I ＆ C （instrumentation and control） system in nuclear power plants. FPGAs are highlighted as an alternative means for obsolete control systems. When engineers design the control system of NPPs （nuclear power plants） with FPGAs, it is important to meet the system development life cycles and conduct the verification and validation activities regarding to FPGA-based applications for use in NPPs. Because the verification and validation process is more important than the design process, engineer should consider the characteristics of FPGA, HDL （hardware description language） programming, faults mode, and optimization technique. And also these characteristics should be reflected in verification and validation activities. As a minimum requirement, system designers require that HDL-programmed applications should be developed in accordance with system development life cycle and HPD design process. In the verification and validation processes, a review, test, and analysis activities should be properly conducted.

基于FPGA的电力电子恒导纳开关模型修正算法及实时仿真架构

电力电子实时仿真是目前电力电子系统研究过程中的重要工具。为设计一套经济、可靠的电力电子实时仿真系统,文中搭建了一个以现场可编程门阵列(FPGA)为计算核心的硬件平台,并提出了配套的电磁仿真算法和FPGA架构设计。首先,推导了一种简洁电磁暂态程序(EMTP)算法,用于提高传统离线算法的并行度。其次,从数值算法的角度分析恒导纳开关模型的虚拟功率损耗问题,提出了一种初始误差修正算法,消除了功率损耗。再次,串联以上算法,设计了一种基于状态机框架的数字信号处理(DSP)硬核资源复用FPGA架构,以硬件资源复用的方式实现了资源的高效利用,在不损失速度的同时提高了FPGA的利用效率。最后,通过多个实时仿真算例验证了所提方法的有效性和正确性。

Review of semiconductor devices and other power electronics components at cryogenic temperature

With the increasing demand for high power density,and to meet extreme working conditions,research has been focused on inves-tigating the performance of power electronics devices at cryogenic temperatures.The aim of this paper is to review the performance of power semiconductor devices,passive components,gate drivers,sensors,and eventually power electronics converters at cryogenic temperatures.By comparing the physical properties of semiconductor materials and the electrical performance of commercial power semiconductor devices,silicon carbide switches show obvious disadvantages due to the increased on-resistance and switching time at cryogenic temperature.In contrast,silicon and gallium nitride devices exhibit improved performance when tem-perature is decreased.The performance ceiling of power semiconductor devices can be influenced by gate drivers,within which the commercial alternatives show deteriorated performance at cryogenic temperature compared to room temperature.Moreover,options for voltage and current sense in cryogenic environments are justified.Based on the cryogenic performance of the various components afore-discussed,this paper ends by presenting an overview of the published converter,which are either partially or fully tested in a cryogenic environment.

A Radiation Hardened Power Device——VDMNOSFET

A radiation hardened N channel Si power device——VDMNOSFET (Vertical Double Diffused Metal Nitride Oxide Semiconductor Field Effect Transistor) is fabricated by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.The effects of ionizing radiation and transient high dose rate radiation of the power VDMNOSFET are also presented.Good radiation hardening performance is obtained,compared with the conventional power VDMOSFET.For the specified 200V VDMNOSFET,the threshold voltage shifts is only -0 5V at a Gamma dose of 1Mrad(Si) with +10V gate bias;the transconductance is degraded by 10% at a Gamma dose of 1Mrad(Si);and no burnout failures occur at the transient high dose rate of 1×10 12 rad(Si)/s.It is demonstrated that the ionizing radiation tolerance and burnout susceptibilities of the power MOSFET are improved significantly by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.

基于多FPGA的电力电子实时仿真系统

大功率复杂电力电子装置通常需要实时仿真系统来加速装置开发和功能验证。然而,商业化电力电子实时仿真系统均由国外公司垄断,价格昂贵,系统升级维护费用高,开放性差,仿真容量和接口数量也受限。为此,文中提出了一种基于多现场可编程门阵列(FPGA)的实时仿真系统的实现架构,以多片FPGA作为并行核心运算单元,有效增加仿真容量和缩短仿真步长。分析了数据实时传输的需求,并提出了一种满足通信需求的增强型串行外设接口(SPI)通信方式。基于该架构自主开发研制了实时仿真平台,并采用硬件描述语言构建10kV 12级联H桥静止同步补偿器(STATCOM)电路模型进行系统实时仿真验证。实验结果表明:实时仿真步长可以达到2μs,实时仿真波形与MATLAB仿真波形误差在0.5%以内。

一种抗相关功耗攻击DES算法及FPGA电路实现

针对目前以差分功耗攻击为代表的旁路攻击技术对加密设备的安全性造成了严重威胁的状况,提出了一种基于"非对称"掩码的新型抗差分功耗攻击的方法,并在标准加密算法(DES)中实现.即通过在算法的不同时刻引入不同的随机掩码变换,使加密设备的功耗与密钥之间的相关性被扰乱,从而抵御相关功耗攻击.以此方案设计了电路并采用FPGA实现了电路.搭建了功耗攻击的FPGA实物平台,分别对未加防御的DES和抗相关功耗攻击DES算法电路进行相关功耗攻击实验.实验结果表明,以增大5倍攻击样本且花费了近5倍的破译时间为代价,仍无法攻破该方法保护的DES算法,可见"非对称"掩码方法对相关功耗攻击起到了防御效果.

单相电力锁相环的改进和FPGA实现

针对单相电能锁相环(Phase-Locked Loop,简称PLL)控制方法以及基于可编程逻辑门阵列(Field Programmable Gate Arrays,简称FPGA)实现方法进行了研究。采用硬件描述语言verilog实现了周期积分器、PI调节器以及正余弦模块等单相锁相环控制的所有模块。软件分析结果证明,这种锁相环控制方法能够快速地锁住电网基波相位,具有较高的抗谐波干扰能力。基于FPGA的实验结果证明,在单相输入严重畸变的情况下,系统不仅能够很好地锁住基波相位,而且在输入相位发生突变时,还能够很快地对信号相位重新进行锁定。这种控制方法能够适应单相柔性输电系统(Flexible AC Transmission Systems,简称FACTS)中对电压相位准确性的要求。