Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation

A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.

Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Effect of depositing PCBM on perovskite-based metal–oxide–semiconductor field effect transistors

In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.

Stacked lateral double-diffused metal–oxide–semiconductor field effect transistor with enhanced depletion effect by surface substrate

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Progress of power field effect transistor based on ultra-wide bandgap Ga_2O_3 semiconductor material

As a promising ultra-wide bandgap semiconductor, gallium oxide(Ga_2O_3) has attracted increasing attention in recent years. The high theoretical breakdown electrical field(8 MV/cm), ultra-wide bandgap(～ 4.8 eV) and large Baliga's figure of merit(BFOM) of Ga_2O_3 make it a potential candidate material for next generation high-power electronics, including diode and field effect transistor(FET). In this paper, we introduce the basic physical properties of Ga_2O_3 single crystal, and review the recent research process of Ga_2O_3 based field effect transistors. Furthermore, various structures of FETs have been summarized and compared, and the potential of Ga_2O_3 is preliminary revealed. Finally, the prospect of the Ga_2O_3 based FET for power electronics application is analyzed.

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

SiC MOSFET高温栅氧可靠性研究

碳化硅SiC(silicon carbide)具有优良的电学和热学特性,是一种前景广阔的宽禁带半导体材料。SiC材料制成的功率MOSFET(metal-oxide-semiconductor field-effect transistor)非常适合应用于大功率领域,而高温栅氧可靠性是大功率MOSFET最需要关注的特性之一。通过正压高温栅偏试验和负压高温栅偏试验对比了自研SiC MOSFET和国外同规格SiC MOSFET的高温栅氧可靠性。负压高温栅偏试验结果显示自研SiC MOSFET与国外SiC MOSFET的阈值电压偏移量基本相等,阈值电压偏移量百分比最大相差在4.52%左右。正压高温栅偏试验的结果显示自研SiC MOSFET的阈值电压偏移量较小,与国外SiC MOSFET相比,自研SiC MOSFET的阈值电压偏移量百分比最大相差11%。自研器件占优势的原因是在SiC/SiO2界面处引入了适量的氮元素,钝化界面缺陷的同时,减少了快界面态的产生,使总的界面态密度被降到最低。

SiC MOSFET驱动特性及器件国产化后的影响分析

碳化硅金属氧化物半导体场效应晶体管SiC MOSFET(silicon carbide metal-oxide-semiconductor field-effect transistor)作为一种新型、广泛应用的开关器件,在实际应用中具有更快的开关速度和更低的器件损耗,可以提高变换器的效率,体现更好的性能。针对SiC MOSFET驱动特性,分析寄生参数对其的影响;搭建双脉冲实验平台,分析栅源电压与SiC MOSFET导通时间的关系;针对现有国产SiC MOSFET存在的不足之处,基于搭建的实验平台及其他电源产品,对SiC MOSFET进行国产化器件替代后导通时间、驱动损耗及负压幅值变化的相关分析。

车用碳化硅功率模块的电热性能优化与评估

由于在开关速度、温度特性和耐压能力等方面的优势,SiC(silicon carbide)功率模块开始逐步应用于电动汽车的电机控制器。电机控制器是电动汽车的核心部件,对功率模块的电热特性要求较高,因此对SiC封装提出了很大的挑战。以主流的HybridPACK Drive模块封装为例,优化设计了模块的驱动回路和DBC(direct bonded copper)布局,并引入了铜线键合技术,协同优化了模块的电热性能和可靠性。此外,采用响应面法优化了椭圆形Pin-Fin散热基板,提升了模块的散热性能。最后,分别制造了优化前、后的SiC功率模块样机作为对比,搭建了双脉冲和功率对拖实验平台,评估了2种方案的电热性能。实验结果显示,当芯片交错距离为芯片宽度的1/2时,所优化的功率模块可以在兼顾电性能的同时,实现更优异的热性能。

动态高温反偏应力下的SiC MOSFET测试平台及其退化机理研究

为研究SiC MOSFET在动态漏源应力下的退化机理,开发了一种具有dVds/dt可调功能、最高可达80 V/ns的动态反向偏置测试平台。针对商用SiC MOSFET进行动态高温反偏实验,讨论高电压变化率的动态漏源应力对SiC MOSFET电学特性的影响。实验结果显示,器件的阈值电压和体二极管正向导通电压增加,说明器件JFET区上方的栅氧层和体二极管可能发生了退化。通过Sentaurus TCAD分析了在高漏源电压及高电压变化率下平面栅型SiC MOSFET的薄弱位置,在栅氧层交界处和体二极管区域设置了空穴陷阱,模拟动态高温反偏对SiC MOSFET动静态参数的影响。

计及非线性寄生参数的SiC MOSFET开关暂态模型

针对SiC分析模型忽略高频欠阻尼振荡和非线性寄生参数,导致开关暂态电压/电流误差较大的问题,提出一种计及非线性寄生参数的SiC金属-氧化物半导体场效应晶体管(MOSFET)开关暂态分析模型。首先,根据SiC器件开关过程不同状态建立状态方程。其次,提取非线性结电容和沟道电流变化曲线。基于离散状态变量分析方法,实现状态方程间的转换和非线性寄生参数的更新。最后,将状态方程的迭代输出结果以受控电压源/电流源的形式转换为相应的电路输出,实现计及非线性寄生参数的SiC MOSFET器件开关暂态分析建模,通过双脉冲实验对分析模型开关特性进行验证。

双沟槽SiC金属-氧化物-半导体型场效应管重离子单粒子效应

本文针对第四代双沟槽型碳化硅场效应晶体管升展了不同源漏偏置电压下208 MeV锗离子辐照实验,分析了器件产生单粒子效应的物理机制.实验结果表明,辐照过程中随着初始偏置电压的增大,器件漏极电流增长更明显;在偏置电压为400 V时,重离子注量达到9×10^(4)ion/cm^(2),器件发生单粒子烧毁,在偏置电压为500 V时,重离子注量达到3×10^(4)ion/cm^(2),器件发生单粒子烧毁,单粒子烧毁阈值电压在器件额定工作电压的34%(400 V)以下.对辐照后器件进行栅特性测试,辐照过程中偏置电压为100 V的器件泄漏电流无明显变化;200 V和300 V时,器件的栅极泄漏电流和漏极泄漏电流都增大.结合TCAD仿真模拟进一步分析器件单粒子效应微观机制,结果表明在低偏压下,泄漏电流增大是因为电场集中在栅氧化层的拐角处,导致了氧化层的损伤;在高偏压下,辐照过程中N-外延层和N+衬底交界处发生的电场强度增大,引起显著的碰撞电离,由碰撞电离产生的局域大电流密度导致晶格温度超过碳化硅的熔点,最终引起单粒子烧毁.

SiC MOSFET的质子单粒子效应

SiC金属氧化物半导体场效应晶体管(MOSFET)在深空探测领域具有广阔的应用前景,但空间质子引发的单粒子效应(SEE)对航天器稳定运行造成了严重威胁。对平面栅结构与非对称沟槽栅结构的SiC MOSFET进行了能量为70、100与200 MeV的质子辐照实验。实验结果表明,两种SiC MOSFET的单粒子烧毁(SEB)阈值电压均大于额定漏源电压的75%;SEB阈值电压随质子能量升高而降低。对两种器件进行辐照后栅应力测试发现,两种结构的器件由于沟道不同而对栅应力的响应存在差异;不同的质子能量会在栅极引入不同程度的辐射损伤,低能质子更容易在栅氧化层发生碰撞而引入氧化物潜在损伤。该研究可为揭示SiC MOSFET质子SEE机理和评估抗辐射能力提供参考。

SiC MOSFET器件栅氧可靠性研究综述

碳化硅金属氧化物半导体场效应晶体管SiC MOSFET(silicon carbide metal-oxide-semiconductor field effect transistor)因具有高压、高频、低导通损耗等优异特性而获得产业界广泛关注,但相比于硅基IGBT,SiC/SiO_(2)栅氧界面高缺陷密度引起的栅氧可靠性问题成为制约SiC MOSFET器件规模化应用的关键瓶颈。通过对近年来国内外SiC MOSFET栅氧可靠性研究成果的梳理和分析,阐述了当前栅氧可靠性问题的形成原因,归纳总结了各类常用的栅氧可靠性评估方法,并进行了比较分析,最后重点探讨了极端工况下SiC MOSFET栅氧可靠性及其提升技术的发展现状。