Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

SPICE model of trench-gate MOSFET device

A novel simulation program with an integrated circuit emphasis（SPICE） model developed for trench-gate metal-oxide-semiconductor field-effect transistor（M OSFET）devices is proposed. The drift region resistance was modeled according to the physical characteristics and the specific structure of the trench-gate MOSFET device. For the accurate simulation of dynamic characteristics, three important capacitances, gate-to-drain capacitance Cgd, gate-to-source capacitance Cgsand drain-to-source capacitance Cds, were modeled, respectively, in the proposed model. Furthermore,the self-heating effect, temperature effect and breakdown characteristic were taken into account; the self-heating model and breakdown model were built in the proposed model; and the temperature parameters of the model were revised. The proposed model is verified by experimental results, and the errors between measured data and simulation results of the novel model are less than 5%. Therefore, the model can give an accurate description for both the static and dynamic characteristics of the trench-gate MOSFET device.

基于LSTM-DHMM的MOSFET器件健康状态识别与故障时间预测

针对MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)器件故障预测与健康管理问题,提出了一种长短时记忆(Long Short-Term Memory,LSTM)算法与离散隐马尔可夫模型(Discrete Hidden Markov Model,DHMM)相结合的故障预测新方法.该方法利用LSTM算法预测器件状态发展趋势;用自回归(AutoRegressive,AR)模型提取故障信息特征;以DHMM建立特征向量和退化等级之间的映射关系;在LSTM-DHMM模型预测结果的基础上,结合失效阈值排除虚警并预测故障时间,预测误差小于10%,精度较高.与GRU-DHMM(Gated Recurrent Unit Discrete Hidden Markov Model)、GRU-SVM(Gated Recurrent Unit Support Vector Machine)、LSTM-SVM(Long Short-Term Memory Support Vector Machine)方法进行对比分析,结果表明,LSTM-DHMM的预测准确率高于其他三种方案,能有效识别实验器件健康状态、较好预测故障时间,具有有效性和优越性.

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.

1200V/30 A SiC MOSFET的结构设计与特性仿真

4H-SiC金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistor,MOSFET)具有开关频率高、功率密度大、耐高温、抗辐照等优点,在军用和民用领域具有广阔的应用前景。针对漏源击穿电压1 200 V的设计目标,利用解析模型和数值仿真相结合的优化方法,通过分析元胞结构参数对器件电学特性的影响,确定4H-Si C MOSFET元胞的纵向与横向结构参数。仿真结果表明,优化设计的器件其特征导通电阻为4.75 m?·cm2,击穿电压为1 517 V,满足设计指标。

Strain induced changes in performance of strained-Si/strained-Si1-yGey/relaxed-Si1-xGex MOSFETs and circuits for digital applications

Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Sub-5 nm bilayer GaSe MOSFETs towards ultrahigh on-state current

Dielectric engineering plays a crucial role in the process of device miniaturization.Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors(MOSFETs),considering hetero-gate-dielectric construction,dielectric materials and GaSe stacking pattern.The results show that device performance strongly depends on the dielectric constants and locations of insulators.When highk dielectric is placed close to the drain,it behaves with a larger on-state current(I_(on))of 5052μA/μm when the channel is 5 nm.Additionally,when the channel is 5 nm and insulator is HfO2,the largest I_(on) is 5134μA/μm for devices with AC stacking GaSe channel.In particular,when the gate length is 2 nm,it still meets the HP requirements of ITRS 2028 for the device with AA stacking when high-k dielectric is used.Hence,the work provides guidance to regulate the performance of the two-dimensional nanodevices by dielectric engineering.

基于第一性原理的碳化硅界面态机制研究进展

碳化硅(SiC)金属–氧化物–半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)具有低导通电阻及高击穿临界场强等特点,在高压开关器件领域有着较为广阔的应用及发展前景。但由于SiC/SiO_2具有较高的界面态密度,使得器件反型沟道电子迁移率过低,从而严重阻碍SiC器件的广泛应用。为有效地控制界面态,回顾了国内外对SiC/SiO_2界面态的第一性原理研究进展,分析界面态的形成机制,讨论近导带边界中高界面态的根本原因,为SiC器件工艺制备提供理论指导。

Negative Resistance Region 10 nm Gate Length on FINFET

In this paper the physical characteristics of FINFET (fin-field effect transistor) transistor behavior are investigated. For the analysis, semi-classical electron transfer method was used based on drift diffusion approximation by TCAD (Tiber CAD) software. Simulations show that the output resistance of FINFET along very small gate (gate length and fin height of 50 nm) is negative. The negative resistance is used in oscillators.

Device performance limit of monolayer SnSe_(2) MOSFET

Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(ML)SnSe_(2),as an abundant,economic,nontoxic,and stable two-dimensional material,possesses an anisotropic electronic nature.Herein,we study the device performances of the ML SnSe_(2) metal-oxide-semiconductor FETs(MOSFETs)and deduce their performance limit to an ultrashort gate length(L_(g))and ultralow supply voltage(V_(dd))by using the ab initio quantum transport simulation.An ultrahigh I_(on) of 5,660 and 3,145µA/µm is acquired for the n-type 10-nm-L_(g) ML SnSe_(2) MOSFET at V_(dd)=0.7 V for high-performance(HP)and low-power(LP)applications,respectively.Specifically,until L_(g) scales down to 2 and 3 nm,the MOSFETs(at V_(dd)=0.65 V)surpass I_(on),intrinsic delay time(τ),and power-delay product(PDP)of the International Roadmap for Device and Systems(IRDS,2020 version)for HP and LP devices for the year 2028.Moreover,the 5-nm-L_(g) ML SnSe_(2) MOSFET(at V_(dd)=0.4 V)fulfills the IRDS HP device and the 7-nm-L_(g) MOSFET(at V_(dd)=0.55 V)fulfills the IRDS LP device for the year 2034.