A Beidou 3(BD3)system-based power reference station can provide high-precision time synchronization for power distribution systems by sending synchronization data packets to devices in a multi-hop routing fashion.Howe...A Beidou 3(BD3)system-based power reference station can provide high-precision time synchronization for power distribution systems by sending synchronization data packets to devices in a multi-hop routing fashion.However,optimizing route selection to reduce both time synchronization error and delay is a challenging problem.In this paper,we establish a software-defined network-enabled power reference station time synchronization framework based on BD3.Then,we formulate the joint problem to minimize cumulative synchronization error and delay through multi-hop route selection optimization.A back propagation(BP)neural network-improved intelligent time synchronization route selection algorithm named BP-RS is proposed to learn the optimal route selection,which uses a BP neural network to dynamically adjust the exploration factor to achieve rapid convergence.Simulation results show the superior performance of BP-RS in synchronization delay,synchronization error,and adaptability with changing routing topologies.展开更多
To solve the coverage and quality problems caused by cell outage in LTE networks, this paper proposes a distributed self-organizing networks management architecture and a distributed cell outage compensation managemen...To solve the coverage and quality problems caused by cell outage in LTE networks, this paper proposes a distributed self-organizing networks management architecture and a distributed cell outage compensation management mechanism. After detecting and analyzing the outage, a cell outage compensation algorithm based on reference signal power adjustment is proposed. The simulation results show that the proposed mechanism can mitigate the performance degradation significantly. Compared with other algorithms, the proposed scheme is more effective in compensating the coverage gap induced by cell outage展开更多
Featuring low communication requirements and high reliability,the voltage droop control method is widely adopted in the voltage source converter based multi-terminal direct current(VSC-MTDC)system for autonomous DC vo...Featuring low communication requirements and high reliability,the voltage droop control method is widely adopted in the voltage source converter based multi-terminal direct current(VSC-MTDC)system for autonomous DC voltage regulation and power-sharing.However,the traditional voltage droop control method with fixed droop gain is criticized for over-limit DC voltage deviation in case of large power disturbances,which can threaten stable operation of the entire VSCMTDC system.To tackle this problem,this paper proposes an adaptive reference power based voltage droop control method,which changes the reference power to compensate the power deviation for droop-controlled voltage source converters(VSCs).Besides retaining the merits of the traditional voltage droop control method,both DC voltage deviation reduction and power distribution improvement can be achieved by utilizing local information and a specific control factor in the proposed method.Basic principles and key features of the proposed method are described.Detailed analyses on the effects of the control factor on DC voltage deviation and imbalanced power-sharing are discussed,and the selection principle of the control factor is proposed.Finally,the effectiveness of the proposed method is validated by the simulations on a five-terminal VSC based high-voltage direct current(VSC-HVDC)system.展开更多
This work proposes an alternative strategy to the use of a speed sensor in <span style="white-space:normal;font-size:10pt;font-family:;" "="">the implementation of active and reactive po...This work proposes an alternative strategy to the use of a speed sensor in <span style="white-space:normal;font-size:10pt;font-family:;" "="">the implementation of active and reactive power based model reference adaptive system (PQ-MRAS) estimator in order to calculate the rotor and stator resistances of an induction motor (IM) and the use of these parameters for the detection of inter-turn short circuits (ITSC) faults in the stator of this motor. The rotor and stator resistance estimation part of the IM is performed by the PQ-MRAS method in which the rotor angular velocity is reconstructed from the interconnected high gain observer (IHGO). The ITSC fault detection part is done by the derivation of stator resistance estimated by the PQ-</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">MRAS estimator. In addition to the speed sensorless detection of ITSC faults of the IM, an approach to determine the number of shorted turns based on the difference between the phase current of the healthy and faulty machine is proposed. Simulation results obtained from the MATLAB/Simulink platform have shown that the PQ-MRAS estimator using an interconnected high-</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">gain observer gives very similar results to those using the speed sensor. The </span><span style="white-space:normal;font-size:10pt;font-family:;" "="">estimation errors in the cases of speed variation and load torque are al</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">mos</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">t identical. Variations in stator and rotor resistances influence the per</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">formance of the observer and lead to poor estimation of the rotor resistance. The results of ITSC fault detection using IHGO are very similar to the results in the literature using the same diagnostic approach with a speed sensor.</span>展开更多
This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power c...This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.展开更多
This paper proposes a novel high-power supply rejection ratio(high-PSRR) high-order curvature-compensated CMOS bandgap voltage reference(BGR) in SMIC 0.18 μm CMOS process. Three kinds of current are added to a co...This paper proposes a novel high-power supply rejection ratio(high-PSRR) high-order curvature-compensated CMOS bandgap voltage reference(BGR) in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^(1.5) current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^(-6)′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.展开更多
基金supported by the Science and Technology Project of the China Southern Power Grid Company Limited under grant number GDKJXM20202032。
文摘A Beidou 3(BD3)system-based power reference station can provide high-precision time synchronization for power distribution systems by sending synchronization data packets to devices in a multi-hop routing fashion.However,optimizing route selection to reduce both time synchronization error and delay is a challenging problem.In this paper,we establish a software-defined network-enabled power reference station time synchronization framework based on BD3.Then,we formulate the joint problem to minimize cumulative synchronization error and delay through multi-hop route selection optimization.A back propagation(BP)neural network-improved intelligent time synchronization route selection algorithm named BP-RS is proposed to learn the optimal route selection,which uses a BP neural network to dynamically adjust the exploration factor to achieve rapid convergence.Simulation results show the superior performance of BP-RS in synchronization delay,synchronization error,and adaptability with changing routing topologies.
文摘To solve the coverage and quality problems caused by cell outage in LTE networks, this paper proposes a distributed self-organizing networks management architecture and a distributed cell outage compensation management mechanism. After detecting and analyzing the outage, a cell outage compensation algorithm based on reference signal power adjustment is proposed. The simulation results show that the proposed mechanism can mitigate the performance degradation significantly. Compared with other algorithms, the proposed scheme is more effective in compensating the coverage gap induced by cell outage
基金supported by the Key Science and Technology Projects of China Southern Power Grid Corporation(No.090000KK52180116)National Natural Science Foundation of China(No.51807135)。
文摘Featuring low communication requirements and high reliability,the voltage droop control method is widely adopted in the voltage source converter based multi-terminal direct current(VSC-MTDC)system for autonomous DC voltage regulation and power-sharing.However,the traditional voltage droop control method with fixed droop gain is criticized for over-limit DC voltage deviation in case of large power disturbances,which can threaten stable operation of the entire VSCMTDC system.To tackle this problem,this paper proposes an adaptive reference power based voltage droop control method,which changes the reference power to compensate the power deviation for droop-controlled voltage source converters(VSCs).Besides retaining the merits of the traditional voltage droop control method,both DC voltage deviation reduction and power distribution improvement can be achieved by utilizing local information and a specific control factor in the proposed method.Basic principles and key features of the proposed method are described.Detailed analyses on the effects of the control factor on DC voltage deviation and imbalanced power-sharing are discussed,and the selection principle of the control factor is proposed.Finally,the effectiveness of the proposed method is validated by the simulations on a five-terminal VSC based high-voltage direct current(VSC-HVDC)system.
文摘This work proposes an alternative strategy to the use of a speed sensor in <span style="white-space:normal;font-size:10pt;font-family:;" "="">the implementation of active and reactive power based model reference adaptive system (PQ-MRAS) estimator in order to calculate the rotor and stator resistances of an induction motor (IM) and the use of these parameters for the detection of inter-turn short circuits (ITSC) faults in the stator of this motor. The rotor and stator resistance estimation part of the IM is performed by the PQ-MRAS method in which the rotor angular velocity is reconstructed from the interconnected high gain observer (IHGO). The ITSC fault detection part is done by the derivation of stator resistance estimated by the PQ-</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">MRAS estimator. In addition to the speed sensorless detection of ITSC faults of the IM, an approach to determine the number of shorted turns based on the difference between the phase current of the healthy and faulty machine is proposed. Simulation results obtained from the MATLAB/Simulink platform have shown that the PQ-MRAS estimator using an interconnected high-</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">gain observer gives very similar results to those using the speed sensor. The </span><span style="white-space:normal;font-size:10pt;font-family:;" "="">estimation errors in the cases of speed variation and load torque are al</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">mos</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">t identical. Variations in stator and rotor resistances influence the per</span><span style="white-space:normal;font-size:10pt;font-family:;" "="">formance of the observer and lead to poor estimation of the rotor resistance. The results of ITSC fault detection using IHGO are very similar to the results in the literature using the same diagnostic approach with a speed sensor.</span>
基金supported by the Shenzhen Key Laboratory Development Project,China(No.CXB201104210007A)
文摘This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.
基金supported by the National Natural Science Foundation of China (61471075, 61301124)the 2013 Program for Innovation Team Building at Institutions of Higher Education in Chongqing (the Innovation Team of Smart Medical System and Key Technology)
文摘This paper proposes a novel high-power supply rejection ratio(high-PSRR) high-order curvature-compensated CMOS bandgap voltage reference(BGR) in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^(1.5) current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^(-6)′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.