Progress of power field effect transistor based on ultra-wide bandgap Ga_2O_3 semiconductor material

As a promising ultra-wide bandgap semiconductor, gallium oxide(Ga_2O_3) has attracted increasing attention in recent years. The high theoretical breakdown electrical field(8 MV/cm), ultra-wide bandgap(～ 4.8 eV) and large Baliga's figure of merit(BFOM) of Ga_2O_3 make it a potential candidate material for next generation high-power electronics, including diode and field effect transistor(FET). In this paper, we introduce the basic physical properties of Ga_2O_3 single crystal, and review the recent research process of Ga_2O_3 based field effect transistors. Furthermore, various structures of FETs have been summarized and compared, and the potential of Ga_2O_3 is preliminary revealed. Finally, the prospect of the Ga_2O_3 based FET for power electronics application is analyzed.

Damage effects and mechanism of the silicon NPN monolithic composite transistor induced by high-power microwaves

A two-dimensional model of the silicon NPN monolithic composite transistor is established for the first time by utilizing the semiconductor device simulator, Sentaurus-TCAD. By analyzing the internal distributions of electric field, current density, and temperature of the device, a detailed investigation on the damage process and mechanism induced by high-power microwaves （HPM） is performed. The results indicate that the temperature elevation occurs in the negative half-period and the temperature drop process is in the positive half-period under the HPM injection from the output port. The damage point is located near the edge of the base-emitter junction of T2, while with the input injection it exists between the base and the emitter of T2. Comparing these two kinds of injection, the input injection is more likely to damage the device than the output injection. The dependences of the damage energy threshold and the damage power threshold causing the device failure on the pulse-width are obtained, and the formulas obtained have the same form as the experimental equations, which demonstrates that more power is required to destroy the device if the pulse-width is shorter. Furthermore, the simulation result in this paper has a good coincidence with the experimental result.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.

Thermal resistance matrix representation of thermal effects and thermal design in multi-finger power heterojunction bipolar transistors

The thermal resistance matrix including self-heating thermal resistance and thermal coupling resistance is presented to describe the thermal effects of multi-finger power heterojunction bipolar transistors. The dependence of thermal resistance matrix on finger spacing is also investigated. It is shown that both self-heating thermal resistance and thermal coupling resistance are lowered by increasing the finger spacing, in which the downward dissipated heat path is widened and the heat flow from adjacent fingers is effectively suppressed. The decrease of self-heating thermal resistance and thermal coupling resistance is helpful for improving the thermal stability of power devices. Furthermore, with the aid of the thermal resistance matrix a 10-finger power heterojunction bipolar transistor （HBT） with non-uniform finger spacing is designed for high thermal stability. The optimized structure can effectively lower the peak temperature while maintaining a uniformity of the temperature profile at various biases and thus the device effectively may operate at a higher power level.

Designing power heterojunction bipolar transistors with non-uniform emitter finger lengths to achieve high thermal stability

With the aid of a thermal-electrical model, a practical method for designing multi-finger power heterojunction bipolar transistors with finger lengths divided in groups is proposed. The method can effectively enhance the thermal stability of the devices without sacrificing the design time. Taking a 40-finger heterojunction bipolar transistor for example, the device with non-uniform emitter finger lengths is optimized and fabricated. Both the theoretical and the experimental results show that, for the optimum device, the peak temperature is lowered by 26.19 K and the maximum temperature difference is reduced by 56.67% when compared with the conventional heterojunction bipolar transistor with uniform emitter finger length. Furthermore, the ability to improve the uniformity of the temperature profile and to expand the thermal stable operation range is strengthened as the power level increases, which is ascribed to the improvement of the thermal resistance in the optimum device. A detailed design procedure is also summarized to provide a general guide for designing power heterojunction bipolar transistors with non-uniform finger lengths.

Design method for transistor-inverted welding power supplies

From the viewpoint of reliability and practicability, a general design method and the related considerationsfor transistor- inverted welding power supplies are proposed in this paper. The detail contents are composed of the choice ofinverters, the choice and protection of transistors, the determination of inverting frequency, the design of transformers,and the choice of output rectifiers and rectifying diodes. Besides, a concrete design example of the transistor-invertedpower supply for plasma arc cutting is introduced.

大功率射频Si-VDMOS功率晶体管研制

介绍了大功率射频硅-垂直双扩散金属氧化物场效应晶体管(Si-VDMOS)的研制结果,采用栅分离降低反馈电容技术、多子胞降低源极电感技术等,从芯片原理着手,比较分析两种芯片结构设计对反馈电容的影响,以及两种布局引线对源极电感的影响,并研制出了百瓦级以上大功率射频Si-VDMOS功率晶体管系列产品。产品主要性能如下:在工作电压28 V及连续波下,采用8胞合成时,225 MHz输出功率达200 W以上,500 MHz输出功率达150 W以上;进一步增加子胞数量,采用12胞合成时,225 MHz输出功率达300 W以上,同时具备良好的增益及效率特性,与国外大功率射频Si-VDMOS功率晶体管的产品参数相比,达到了同类产品水平。

氧化锌锡薄膜晶体管的制备与性能研究

为了提高薄膜晶体管的性能,本文基于射频磁控溅射技术,采用氧化锌锡(ZTO)材料作为沟道层,在SiO2/p-Si衬底上制备高性能ZTO薄膜晶体管。采用AFM、XRD、UV-Vis研究了溅射功率对ZTO薄膜的表面形貌和光学性能的影响。使用半导体参数仪对ZTO薄膜晶体管进行电学性能的测试,利用XPS分析研究溅射功率对ZTO薄膜中元素组成和价态的影响,探索高性能薄膜晶体管的原理机制。实验结果表明,所有ZTO薄膜样品是非晶结构,表面致密,透光率均大于90%。适当增加溅射功率能够改善ZTO薄膜晶体管的电学性能。在90 W溅射功率下制备的薄膜晶体管综合性能较好,其饱和迁移率达到了15.61 cm^(2)/(V·s),亚阈值摆幅为0.30 V/decade,阈值电压为-5.06 V,电流开关比为8.92×10^(9)。

BCD工艺中大电流下纵向双极晶体管的电流集边效应研究

在大电流条件下,随着电流密度的增加,发射区结电流集边效应、基区电导调制效应、基区展宽效应会随之出现。基于研究单位的BCD工艺,在集成CMOS和DMOS的基础上集成功率纵向NPN双极晶体管用于输出。设计了75μm×4μm、50μm×6μm、30μm×10μm三种不同尺寸的发射极并进行TCAD仿真研究。在发射极面积相同的情况下,发射极长宽比越小,TCAD可观察到的电流集边效应越严重,最终流片并进行测试验证,得出75μm×4μm的细长结构尺寸能够提升晶体管在大电流下的放大能力,较30μm×10μm的结构提升约11.4%。

0.2~2.0GHz100W超宽带GaN功率放大器

设计并实现了一款基于0.25μm GaN高电子迁移率晶体管(HEMT)工艺的100 W超宽带功率放大器。基于SiC无源工艺设计了集成无源器件(IPD)输入预匹配电路芯片;设计了基于陶瓷基片的T型集成输出预匹配电路;基于建立的传输线变压器(TLT)的精确模型,设计了宽带阻抗变换器,在超宽频带内将50Ω的端口阻抗变换至约12.5Ω,再通过多节微带电路与预匹配后的GaN HEMT芯片实现阻抗匹配。最终,以较小的电路尺寸实现了功率放大器的超宽带性能指标。测试结果表明,功率放大器在0.2~2.0 GHz频带内,在漏极电压36 V、输入功率9 W、连续波的工作条件下,输出功率大于103 W,漏极效率大于50%,输入电压驻波比(VSWR)≤2.5。

一种双管反激级联式高位取能电源设计

在柔性直流输电系统中,高位取能电源为模块化多电平换流器(MMC)的子模块控制电路供电。随着直流输电系统电压的提升,子模块直流侧的电压也随之升高。为使高位取能电源适应更高更宽范围的输入电压,设计了一种基于双管反激的级联式拓扑。首先,介绍双管反激电路的工作原理、电流控制模式及工作模态;其次,基于变压器初级电流中位值,重新推导变压器AP值公式,与传统AP值方法进行比较;然后,基于南澳柔性直流输电换流阀的相关参数,对电源主电路进行设计。最后,搭建了一台输入电压为350~4 000 V,输出为一路400 V、两路15 V的电源样机,通过实验结果验证了设计的有效性和分析的正确性。

基于Marx电路的固态高压脉冲电源设计

针对高压脉冲放电和低温等离子体应用的要求,设计了一种基于Marx电路的高重复频率的固态高压脉冲发生装置。该脉冲电源利用Marx电路电容并联充电、串联放电的原理,选取绝缘栅双极型晶体管(IGBT)作为放电开关,控制电路的模态切换。Marx主电路由84级单元组成,每级单元包含IGBT开关管、快恢复二极管和储能电容。实验结果表明,在输入电压为480 V直流电压,并且在300 Hz的频率下,该电源可以产生幅值为20 kV、脉宽为500 ns的高压脉冲,满足设计要求。

功率三级管热带海洋-寒冷环境时序影响效应分析

为了研究功率三极管在热带海洋-寒冷环境时序影响效应,采用热带海洋环境和寒冷环境时序试验的方法,将试验件放置于棚下机箱内模拟其使用环境,开展自然环境试验工作。试验过程中,定期对样品分析其外观及功能性能变化情况,样品在完成5个月寒冷大气和5个月热带海洋环境试验后,出现致使ICBO和ICEO参数超差现象,通过失效分析发现,导致功率三级管失效的原因为CI离子引起管壳局部腐蚀,生成氧化产物,导致引脚间漏电,上述试验结果可为其热带海洋-寒冷环境适应性设计改进提供技术支撑。

基于电源调制的L波段高性能GaAsHBT功率放大器

介绍了一种基于GaInP/GaAs异质结双极晶体管(HBT)工艺、电源调制的高峰均比、高功率附加效率L波段功率放大器芯片,可满足多载波聚合、大容量通信系统的要求。从器件层面控制基极表面复合、寄生电阻和电容,实现低膝点电压、跨导均匀的晶体管;在电路层面采用自适应偏置电路和谐波调谐等提升线性和功率附加效率。该放大器采用前级驱动加末级输出、驱动比为1∶6的两级晶体管架构和高低通搭配的匹配电路。测试结果表明,在5 V偏置电压下,该功率放大器的饱和输出功率大于35 dBm;在大功率回退时(8 dBm),增益变化小于2 dB,功率附加效率指标达到50%;对于调制带宽为25 kHz的16进制正交振幅调制(16QAM)通信系统,邻道功率比小于-38 dBc@27 dBm。

基于SiGe BiCMOS的全集成射频功率放大器设计

提出了一种基于SiGe BiCMOS工艺的适用于移动设备的紧凑全集成功率放大器.设计采用cascode驱动级与共发射极功率级级联以提高放大器的功率增益,片上集成CMOS电源以提供偏置电流,采用分布式的镇流电阻和具有热负反馈效果的偏置电路补偿结温以防止放大器在高温工作时失效,并且采用一种紧凑的电路级的热耦合模型对所提出的热稳定措施进行仿真验证.后仿结果表明:PA在3.3 V供电下、2.4~2.5 GHz的工作范围内输出增益为32.5 dB,S11&S22<-10 dB,1 dB压缩点处的输出功率为25.4 dBm,在25℃的环境温度下最高结温小于65℃(饱和).芯片面积仅为1.25×0.76 mm^(2).测试结果表明:在-45~85℃的工作环境下,可以在增益要求为26.5~32.9 dB的应用中正常工作.1 dB压缩点处的输出功率为24.3 dBm.采用20 MHz 64-QAM OFDM信号测试,DEVM达到-30 dB的输出功率为18.1 dBm.

一种基于变压器集成的高位取能电源设计

在柔性直流输电系统中,高位取能电源为模块化多电平换流器(MMC)的子模块控制电路供电。目前普遍采用多路输入串联结构来使高位取能电源承受更高更宽范围的输入电压,因此存在电路中磁性元件过多及多路串联是否均压等问题。针对此类问题,设计了一种基于变压器集成式的双管反激拓扑。首先介绍双管反激拓扑结构及其工作模态;其次分析磁集成变压器自均压工作机理并推导磁集成变压器面积乘积(AP)计算公式;然后针对南澳柔性直流输电换流阀相关参数,对电源参数进行设计;最后搭建了一台输入电压为350~4000V的实验样机,实验结果验证了设计的有效性和分析的正确性。

650 V IGBT横向变掺杂终端的设计与优化

绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)器件的最重要参数之一是击穿电压(Breakdown Voltage,BV),影响IGBT器件BV的因素包括:平面工艺PN结扩散终端、界面电荷、杂质在Si、SiO2中具有不同分凝系数等。其中影响IGBT器件耐压能力的重要因素是芯片终端结构的设计,终端区耗尽层边界的曲率半径制约了BV的提升,为了能够减少曲率效应和增大BV,可以采取边缘终端技术。通过Sentaurus TCAD计算机仿真软件,采取横向变掺杂(Variable Lateral Doping,VLD)技术,设计了一款650 V IGBT功率器件终端,在VLD区域利用掩膜技术刻蚀掉一定的硅,形成浅凹陷结构。仿真结果表明,这一结构实现了897 V的耐压,终端长度为256μm,与同等耐压水平的场限环终端结构相比,终端长度减小了19.42%,且最大表面电场强度为1.73×10^(5)V/cm,小于硅的临界击穿电场强度(2.5×10^(5)V/cm);能在极大降低芯片面积的同时提高BV,并且提升了器件主结的耐压能力。此外,工艺步骤无增加,与传统器件制造工艺相兼容。

基于GaAsHBT的C波段RLC负反馈功率放大器设计

提出了一款基于GaAs HBT C波段的线性负反馈功率放大器(power amplifier,PA).本设计采用三级共发射极(common emitter,CE)结构,使用两种不同的有源线性偏置来提升PA的线性度,同时使用RLC负反馈网络来提高稳定性和拓展工作带宽.针对传统的负反馈网络结构PA的增益下降问题,RLC负反馈网络可以通过调整负反馈网络中的电感值来有效减小负反馈带来的增益下降的影响.测试结果表明:室温下,在5.1~7.4 GHz范围内,实现增益大于28 dB.在5.9~7.1 GHz的线性工作频段内,平均增益大约为29.5 dB,S11和S22均小于-10 dB;在满足无线局域网标准802.11a,采用20 MHz 64-QAM信号,EVM达到-30 dB的输出功率为18.9~22.5 dBm.在5.9~6.2 GHz时,饱和输出功率大于30 dBm,最大的附加功率效率大于35%.