Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.

Novel Power-Aware Optimization Methodology and Efficient Task Scheduling Algorithm

The performance of central processing units(CPUs)can be enhanced by integrating multiple cores into a single chip.Cpu performance can be improved by allocating the tasks using intelligent strategy.If Small tasks wait for long time or executes for long time,then CPU consumes more power.Thus,the amount of power consumed by CPUs can be reduced without increasing the frequency.Lines are used to connect cores,which are organized together to form a network called network on chips(NOCs).NOCs are mainly used in the design of processors.However,its performance can still be enhanced by reducing power consumption.The main problem lies with task scheduling,which fully utilizes the network.Here,we propose a novel randomfit algorithm for NOCs based on power-aware optimization.In this algorithm,tasks that are under the same application are mapped to the neighborhoods of the same application,whereas tasks belonging to different applications are mapped to the processor cores on the basis of a series of steps.This scheduling process is performed during the run time.Experiment results show that the proposed randomfit algorithm reduces the amount of power consumed and increases system performance based on effective scheduling.

Power-Aware Wireless Communication System Design for Body Area Networks

With the explosive development of wireless communication and low power embedded techniques, Body Area Network (BAN) has opened up new frontiers in the race to provide real-time health monitoring. IEEE 802 has established a Task Group called IEEE 802.15.6 inNovember 2007 and aims to establish a communication standard optimized for low power, high reliability applied to medical and non-medical application for BANs. This paper overviews the path loss model and the communication scheme for implant-to-body surface channel presented by IEEE 802.15.6 standard. Comparing with the standard scheme where BCH (Bose-Chaudhuri-Hochquenghem) code is employing, we propose a new coding solution using convolutional code operating with Bit Interleaver based on the properties of implant-to-body surface channel. To analyze the performance of the two Error Correct Coding (ECC) schemes, we performed simulations in terms of Bit Error Rate (BER) and power consumption on MATLAB and FPGA platform, respectively. The simulation results proved that with appropriate constraint length, convolutional code has a better performance not only in BER, but also in minimization of resources and power consumption.

Side-channel attack-resistant AES S-box with hidden subfield inversion and glitch-free masking

A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts.In addition,a delaymatched enable control technique is used to suppress glitches in the masked parts.The evaluation results show that its area is contracted to 63.3%of the full PAH S-box,and its power-delay product is much lower than that of the masking implementation.The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665000 noiseless traces.

Reliable Remote Relay Protection in Smart Grid

As the false trips of remote protection relays are among the main reasons behind cascading blackouts, it is critical to design reliable relay protection. Even though common protection schemes on traditional power systems have been investigated for a few decades, cascading failures in recent years indicate more research needed in this area. Consequently, researchers have proposed agent-based methods on the Smart Grid （SG） to address this issue. However, these existing agent-based methods simply use TCP protocol without considering real-time communication requirements （such as bandwidth and delay）. To deal with this issue, several methods for efficient network resource management are proposed. Furthermore, these existing methods do not consider the potential issues in practical communication networks, which may result in delay violation and trigger relay false trips. We have discussed simple backup solutions in the previous work. In this paper, in addition to network efficiency, we focus on improving the system reliability by exploring known power system information and minimizing the chances of false trips of important remote relays, e.g., defining power line priorities based on their importance. Moreover, to further improve the. system reliability, we also in- vestigate the peer-to-peer protection approaches to address the single point of failure of centralized control center.

Adventures Beyond Amdahl's Law:How Power-Performance Measurement and Modeling at Scale Drive Server and Supercomputer Design

Amdahl’s Law painted a bleak picture for large-scale computing.The implication was that parallelism was limited and therefore so was potential speedup.While Amdahl’s contribution was seminal and important,it drove others vested in parallel processing to define more clearly why large-scale systems are critical to our future and how they fundamentally provide opportunities for speedup beyond Amdahl’s predictions.In the early 2000s,much like Amdahl,we predicted dire consequences for large-scale systems due to power limits.While our early work was often dismissed,the implications were clear to some:power would ultimately limit performance.In this retrospective,we discuss how power-performance measurement and modeling at scale led to contributions that have driven server and supercomputer design for more than a decade.While the influence of these techniques is now indisputable,we discuss their connections,limits and additional research directions necessary to continue the performance gains our industry is accustomed to.

Energy-Aware GPU Programming at Source-Code Levels

To enhance the energy efficiency and performance of algorithms with Graphics Processing Unit （GPU） accelerators in source-code development, we consider the power efficiency based on data transfer bandwidth and power consumption in key situations. First, a set of primitives is abstracted from program statements. Then, data transfer bandwidth and power consumption in different granularity sizes are consid- ered and mapped into proper primitives. With these mappings, a programmer can intuitively determine the power efficiency and performance in different running states of a thread. Finally, this intuition enables the programmer to tune the algorithm in order to achieve the best energy efficiency and performance. Using these power-aware principles, two Fast Fourier Transform （FFT） methods are compared. The mapping be- tween power consumption and primitives is helpful for algorithm tuning in source-code levels.