A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitation...A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61106024)the Natural Science Foundation of Jiangsu Provice,China(No.BK2010411)
文摘A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate （FCG） stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom con- suming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute induc- tors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature （PVT） variation. Two representative sam- ples provide a trans-impedance gain of 53.9 dBf2, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBg2, a 3-dB bandwidth of 8.1 GHz, a power dis- sipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/√Hz. The chip area is only 0.08 x 0.08 mm2.
