This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematica...This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.展开更多
随着量子计算的发展,现有密码系统的安全性将受到严重威胁.Saber算法是抵御量子计算攻击的后量子密码方案之一,但存在多项式商环上模乘占据运算开销过大的问题.鉴此,本文通过对Karatsuba算法和Schoolbook相乘方式的剖析,提出一种面向Sa...随着量子计算的发展,现有密码系统的安全性将受到严重威胁.Saber算法是抵御量子计算攻击的后量子密码方案之一,但存在多项式商环上模乘占据运算开销过大的问题.鉴此,本文通过对Karatsuba算法和Schoolbook相乘方式的剖析,提出一种面向Saber算法的并行乘法器设计方案.该方案首先利用Karatsuba算法分解模乘运算的关键路径,结合乘法复用和加法替换的策略减少硬件开销,然后采用并行运算电路压缩关键运算路径时长,最后在TSMC 65 nm工艺下,利用Modelsim和DC软件仿真验证.结果表明:该方案运算时长为137个时钟周期,与传统方式相比速度提升46.50%,功耗为87.83 m W,面积为927.32×10^(3)μm^(2).展开更多
Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathemat...Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutras Nikhilam sutra and Karatsuba algorithm are considered. In this research paper, a novel algorithm for binary multiplication based on Vedic mathematics is designed using bit reduction technique. Though Nikhilam sutra is used for multiplication, it is not used in all applications. Because it is special in multiplication. The remainder is derived from this sutra by reducing the remainder bit size to N-2 bit. Here, the number of bits of the remainder is constantly maintained as N-2 bits. By using Karatsuba algorithm, the overall structure of the multiplier is designed. Unlike the conventional Karatsuba algorithm, the proposed algorithm requires only one multiplier with N-2 bits only. The speed of the proposed algorithm is improved with balancing the area and the power. Even though there is a deviation in lower order bits, this method shows larger difference in higher bit lengths.展开更多
文摘This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.
文摘随着量子计算的发展,现有密码系统的安全性将受到严重威胁.Saber算法是抵御量子计算攻击的后量子密码方案之一,但存在多项式商环上模乘占据运算开销过大的问题.鉴此,本文通过对Karatsuba算法和Schoolbook相乘方式的剖析,提出一种面向Saber算法的并行乘法器设计方案.该方案首先利用Karatsuba算法分解模乘运算的关键路径,结合乘法复用和加法替换的策略减少硬件开销,然后采用并行运算电路压缩关键运算路径时长,最后在TSMC 65 nm工艺下,利用Modelsim和DC软件仿真验证.结果表明:该方案运算时长为137个时钟周期,与传统方式相比速度提升46.50%,功耗为87.83 m W,面积为927.32×10^(3)μm^(2).
文摘Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutras Nikhilam sutra and Karatsuba algorithm are considered. In this research paper, a novel algorithm for binary multiplication based on Vedic mathematics is designed using bit reduction technique. Though Nikhilam sutra is used for multiplication, it is not used in all applications. Because it is special in multiplication. The remainder is derived from this sutra by reducing the remainder bit size to N-2 bit. Here, the number of bits of the remainder is constantly maintained as N-2 bits. By using Karatsuba algorithm, the overall structure of the multiplier is designed. Unlike the conventional Karatsuba algorithm, the proposed algorithm requires only one multiplier with N-2 bits only. The speed of the proposed algorithm is improved with balancing the area and the power. Even though there is a deviation in lower order bits, this method shows larger difference in higher bit lengths.
