Determination AHP Analysis of the Virtual Stage-Gate Process in the Global Scale Automotive Design

In this study, it is aimed to determine the ranking importance levels of the stages to be taken into consideration for new product development on a global scale in the automotive design process. New product design activity and stage-gate process differences between local automotive firms (serial production factory and stage-gate department in Turkey) and global automotive companies (serial production factory and stage-gate department in Turkey) are examined comparatively in the research area. In the automotive industry, which has been developing for a century, the question of how the local company products operating in the last sixty years have not been able to spread globally or how to develop global products is the background question of the research. For this purpose, one on one interviews were held with the managers of 3 national and 3 international automotive companies, who worked in the same region and who had previously designed a new vehicle, with design and product development departments.?According to?the data obtained by the AHP (Analytic Hierarchy Process) in the automotive design process, the importance of the criteria that should be taken into account for global product development has revealed. According to the results of the study, it was found that design validation stages were the most important globalization criterion in automotive design process as a new study area. In the comprehensive survey of the study, no other publication has been encountered to measure or evaluate the stages in the automotive design and new product development process in other sectors, including the vehicle industry. As in every industry sector, in the automotive industry, with the new product companies provide market development or competitive advantage. The new product is the life channel of a company and in the realization of this new vehicle;the disciplines of the automotive industry are formed by a hundred years of experience.

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ？ was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide （TMAH） wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage （～ 0.24 V） for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

Algorithm of Dynamic Operation Process of Hydraulic Automatically Operated Canals with Constant-Downstream Level Gates

On the basis of analysis the governing process of downstream water level gates AVIO and AVIS, a mathematical model for simulation of dynamic operation process of hydraulically automated irrigation canals instalIed with AVIO and AVIS gates is presented, the main point of this rnathematical model is firstly applying a set of unsteady flow equations （St. Venant equations here） and treating the condition of gate movement as its dynamic boundary, and then deeoupling this interaction of gate movement with the change of canal flow. In this process, it is necessary to give the gateg open-loop transfer function whose input is water level deviation and output is gate discharge. The result of this simulation for a practical reach has shown it has satisfactory accuracy.

一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

H-Process浇注系统设计及数值模拟

为实现水平控制浇注逐件充填型腔，设计了一套带浇口盆的浇注系统，其阻流截面在直浇道出口处，直浇道直径30mm，立方体储井棱长85mm，内浇口位于储井底部靠近前壁处，A内：A横：A直=（1-6）：（3．50．0）：1，并利用FLOW-3D软件对其中的金属液流动进行了模拟。结果表明，对铸钢而言，当浇注压头为60～200mm时，金属液逐件充型，整串铸型的浇注条件基本一致，U形横浇道具有较好的集渣作用。

Quantum information processing with nitrogen–vacancy centers in diamond

Nitrogen-vacancy （NV） center in diamond is one of the most promising candidates to implement room temperature quantum computing. In this review, we briefly discuss the working principles and recent experimental progresses of this spin qubit. These results focus on understanding and prolonging center spin coherence, steering and probing spin states with dedicated quantum control techniques, and exploiting the quantum nature of these multi-spin systems, such as superposition and entanglement, to demonstrate the superiority of quantum information processing. Those techniques also stimulate the fast development of NV-based quantum sensing, which is an interdisciplinary field with great potential applications.

Robust scheme for implemention of quantum phase gates for two atoms

We propose a scheme for implementing conditional quantum phase gates for two four-state atoms trapped in a cavity. The two ground states of the atoms are coupled through two Raman processes induced by the cavity mode and two classical fields. Under certain conditions nonresonant Raman processes lead to two-atom coupling and can be used to produce conditional phase gates. The scheme is insensitive to cavity decay, thermal photons, and atomic spontaneous emission. The scheme does not require individual addressing of the atoms.

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

融合Mar-GLSTM的流程生产工艺质量预测算法

针对流程生产连续性强、时序耦合复杂等特点,传统神经网络不具备长期记忆能力,且在深层次网络训练时易出现训练参数灾难、梯度爆炸等问题,提出基于马尔可夫优化的融合门控循环单元(GRU)与长短期记忆网络(LSTM)的组合预测模型(Mar-G LSTM)。首先在循环神经网络结构中融入门控机制构建深度LSTM神经网络模型,对流程生产时序数据信息进行选择性记忆,学习时序数据序列的信息依赖,进而解决训练过程中的梯度爆炸问题;同时结合马尔可夫链对GRU-LSTM模型的预测结果进行修正优化,在降低模型的复杂度的情况下进一步提高了模型的预测精度。最后,结合某流程生产线的工艺数据进行分析验证,结果表明,Mar-G LSTM算法在预测精度上较随机森林模型、门控循环单元神经网络模型(GRU)、长短期记忆神经网络模型(LSTM)和卷积神经网络与门控循环单元网络组合模型(CNN-GRU)分别提高了37.42%、21.32%、17.91%和12.56%,所提Mar-G LSTM算法可实现流程生产质量的准确预测,为降低工艺参数调控任务的完成时间提供了思路和实现途径。

基于现场可编程门阵列的水果识别系统设计

针对目前大多数水果识别系统实时性差和成本较高的问题,本文提出一种基于现场可编程门阵列(FPGA)的水果识别系统。整体硬件设计包含图像采集、检测识别和显示模块。软件部分通过图像采集平台将水果图像存储至双倍数据率同步动态随机存储器(DDR3)控制模块,进行图像灰度化处理,并创造性地提出背景帧差法对水果图像进行分割。通过融合水果颜色和几何特征,实现对水果数量、颜色和种类的识别。整个水果识别系统在不同光照下对常见水果进行了测试。实验结果表明,水果平均识别准确率达到93.25%,识别速度约为16.67 ms,FPGA硬件资源消耗率仅占28.02%,可以满足实时性需求。

基于AHP的城市燃气门站管道风险模糊综合评价方法

为保障城市燃气管道系统的安全平稳运行,本文主要针对城市燃气门站管道因破损、腐蚀、设施失效以及人为因素造成的安全问题,建立一套相对通用的城市燃气门站管道风险评价体系,并利用层次分析法(AHP)确定相关因素的权重,结合模糊综合评价法对城市燃气门站管道风险进行定性、定量分析。本文应用该方法对沈阳市某燃气门站管道进行评价分析,结果表明该门站管道风险等级为低风险,说明本文所建的模型具有实用性。

High performance reconfigurable hardware system for real-time image processing

A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports ＆ serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems （RTOS） by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.

基于偏正结构表示的加工命名实体识别方法

制造企业积累大量的零件加工经验多以文本形式存在,如何从文本中挖掘出高质量的零件加工知识是个尚待解决的问题。针对待识别实体存在的偏正结构特征,导致实体边界界定模糊的问题,提出一种多网络协调的中文命名实体识别方法。在BERT生成字向量的过程中,通过领域自适应方法,提高字向量对工艺实体的表征能力,同时,在BiLSTM-CRF模型中引入注意力机制和多门控制的混合专家网络捕获上下文特征与实体信息。实验表明,较于当前主流的命名实体识别模型,该文提出的方法对机械零件加工实体识别的F1值达到80.15%,取得优于其他模型的最好性能。

Design and Construction of a Digital Multichannel Analyzer for HPGe Detector Using Digital Signal Processing Technique

The outstanding advantage of digital signal processing (DSP) techniques and Field Programmable Gate Array (FPGA) technology is capable of improving the quality of the experimental measurements for nuclear radiation. In this article, a compact DMCA 8 K was designed and manufactured using DSP technique based on FPGA technology. In particular, the output of the preamplifier is completely processed by digital techniques which are obtained from the analog-to-digital converter (ADC) to calculate the baseline, DC offset, energy peaks, pile up, threshold discrimination and then the form of energy spectrum. The Spartan-6 board is used as a hardware for the development of the digital multichannel analyzer (DMCA), which is equipped with the 14-bit AD6645 with 62.5 Msps sample rate. The application software for instrument control, data acquisition and data processing was written under C++ builder via the RS-232 interface. The designed DMCA system has been tested with a HPGe detector using gamma sources of 60Co and 137Cs and a reference pulser.

基于骨架序列的工序动作识别与分析

为了解决工业工程领域传统制造过程中工序动作分析方法存在的耗时耗力与依赖经验的问题,运用动作识别技术替代传统的人工分解动作方法,提出一种基于骨架序列的工序动作智能检测方案。使用2D相机与MediaPipe框架搭建人体姿态估计模型以获取骨架序列,引入相关评估指标进行工序动作量化分析。利用骨架数据构建基于卷积门控循环单元CNN-GRU的动作分类模型,面向自建工序动作数据集进行实验验证。结果表明,所提出的CNN-GRU模型在参数量更少的情况下具有更高的准确率,相较于LSTM模型和GRU模型表现更优。在动作识别的基础上,将所得推理结果与标准作业程序进行对比得出异常动作,为工序动作识别与分析提供有效的解决方案,有助于规范生产操作和提升生产效率。

基于多图超分辨率重建的精细导星仪星点质心定位精度提升方法

精细导星仪的星点质心定位精度决定了空间天文望远镜的视轴姿态解算精度,为了提升精细导星仪的星点质心定位精度,提出了一种基于深度小波循环神经网络的星图超分辨率重建方法。首先,借助微扫描技术获取亚像素错位低分辨率星图序列,采用小波编码器提取低分辨率星图的小波域特征,通过小波系数约束低分辨率星图的噪声,并将亚像素错位星图序列配准过程融入到网络学习中。其次,利用卷积门循环神经单元对所提取的多星图序列特征进行融合。最后,使用逆小波解码器对多特征融合模块输出的小波域特征进行解码,从而实现基于低分辨率星图序列的去噪与超分辨率重建。实验结果表明,分别采用平方加权质心法求取原始星图和超分辨率重建后星图中的各星点的质心位置,相比于前者,后者的各星点平均质心定位精度和稳定度在X方向分别提升了64.76%和19.15%,在Y方向分别提升了75.35%和26.14%。

融合1D-CNN与BiGRU的类不平衡流量异常检测

网络流量异常检测是利用各种检测技术分析判断网络流量,发现网络中潜在的攻击,是一种有效的网络安全防护方法。针对高维海量数据和不同攻击类别的网络流量数据不均衡而导致检测准确率低、误报率高的问题,提出一种融合一维卷积神经网络(1D-CNN)和双向门控循环单元(BiGRU)的类不平衡流量异常检测模型。首先,针对类不平衡数据,通过使用改进的合成少数类过采样技术(SMOTE)即Borderline-SMOTE和基于高斯混合模型(GMM)的欠采样聚类技术进行平衡处理;然后,使用1D-CNN提取数据的局部特征,并利用BiGRU更好地提取数据中的时序特征;最后,在UNSW-NB15数据集对所提模型进行验证,所提模型的准确率为98.12%,误报率为1.28%。结果表明,所提模型提高了对少数攻击的识别率,检测精度高于其他经典机器学习和深度学习模型。

基于图像处理的电路板缺陷检测系统设计

针对传统电路板缺陷检测多为人工检测、速度较慢且成本较高的问题,本文研究设计了一款以图像处理为基础、利用现场可编程门阵列(FPGA)实现对电路板缺陷准确、高速的检测系统。在传统图像增强算法的基础上提出一种针对不同图像信息采用不同感兴趣区间的方法,增强效果显著;为减少电路板上标识字样对匹配算法计算速度的影响,提出一种去除丝印算法,将电路板上多余的标识字样取消,减少图像匹配的计算量,加快检测的速度;在传统绝对误差和算法(SAD)模板匹配算法的基础上采用去平均值法计算图像信息,减小光照变化带来的影响;将传统2算子Sobel边缘检测扩展到8算子边缘检测,边缘信息更加明显清晰。采用FPGA作为硬件平台,在Vivado开发环境下实现Verilog HDL硬件逻辑语言,下载到FPGA中实现。实验结果表明,系统的平均检测精度为98.53%,检测单张电路板的时间为8.204 s。本系统设计在检测精度和速度上都有明显提升,且造价成本低。

基于FPGA的极紫外光谱图像处理系统

东方超环(Experimental Advanced Superconducting Tokamak,EAST)全超导托卡马克装置上极紫外(Extreme Ultraviolet,EUV)光谱诊断系统采用电荷耦合器件(Charge Coupling Device,CCD)探测器集光谱图像数据,硬X射线对CCD产生的干扰造成光谱数据中存在大量的单像素噪声,这为准确分析聚变等离子体杂质辐射带来极大的困难。针对这一问题,设计了一套基于可编程门阵列(Field Programmable Gate Array,FPGA)的EUV光谱图像处理系统,来快速去除硬X射线产生的噪声干扰。该系统基于限幅滤波算法,并引入标准差和离均差替代固定限幅阈值和样本偏差;通过融合限幅滤波算法和数据判别法,外加设置算法工作区间来分阶段对光谱图像数据进行相应处理。同时设计了仿真测试模块,使用EUV光谱图像转化的视频数据模仿采集流程进行系统的功能测试。最后,为了检验该系统对有效光谱数据的保护能力,将图像数据转换成更加直观的谱线图进行对比分析。实验测试结果表明:该系统能够有效去除光谱图像中的噪声点,并较好地保持了光谱数据的完整性,从而提升了光谱数据的可观测性。

面向异构信号处理平台的量子调度算法

针对异构信号处理平台中已有调度算法的调度长度较大导致信号处理应用实时性下降问题,文中提出一种面向异构信号处理平台的量子调度算法。该算法采用任务优先级分流排序策略,得到更加准确的任务调度顺序。使用量子比特对任务分配方案进行编码,增加任务分配方案的多样性,且编码规则有助于跳出局部最优找到全局最优解。按照最小计算开销原则和任务复制思想进行处理器分配,减少任务间通信开销,并通过量子旋转门对量子编码方案进行更新,不断逼近最优解。仿真结果表明,所提算法能够减少调度长度,提升信号处理应用的实时性,进而提高平台的工作效率。