COPPER:a combinatorial optimization problem solver with processing-in-memory architecture

The combinatorial optimization problem(COP),which aims to find the optimal solution in discrete space,is fundamental in various fields.Unfortunately,many COPs are NP-complete,and require much more time to solve as the problem scale increases.Troubled by this,researchers may prefer fast methods even if they are not exact,so approximation algorithms,heuristic algorithms,and machine learning have been proposed.Some works proposed chaotic simulated annealing(CSA)based on the Hopfield neural network and did a good job.However,CSA is not something that current general-purpose processors can handle easily,and there is no special hardware for it.To efficiently perform CSA,we propose a software and hardware co-design.In software,we quantize the weight and output using appropriate bit widths,and then modify the calculations that are not suitable for hardware implementation.In hardware,we design a specialized processing-in-memory hardware architecture named COPPER based on the memristor.COPPER is capable of efficiently running the modified quantized CSA algorithm and supporting the pipeline further acceleration.The results show that COPPER can perform CSA remarkably well in both speed and energy.

ReCSA:a dedicated sort accelerator using ReRAM-based content addressable memory

With the increasing amount of data,there is an urgent need for efficient sorting algorithms to process large data sets.Hardware sorting algorithms have attracted much attention because they can take advantage of different hardware's parallelism.But the traditional hardware sort accelerators suffer“memory wall”problems since their multiple rounds of data transmission between the memory and the processor.In this paper,we utilize the in-situ processing ability of the ReRAM crossbar to design a new ReCAM array that can process the matrix-vector multiplication operation and the vector-scalar comparison in the same array simultaneously.Using this designed ReCAM array,we present ReCSA,which is the first dedicated ReCAM-based sort accelerator.Besides hardware designs,we also develop algorithms to maximize memory utilization and minimize memory exchanges to improve sorting performance.The sorting algorithm in ReCSA can process various data types,such as integer,float,double,and strings.We also present experiments to evaluate the performance and energy efficiency against the state-of-the-art sort accelerators.The experimental results show that ReCSA has 90.92×,46.13×,27.38×,84.57×,and 3.36×speedups against CPU-,GPU-,FPGA-,NDP-,and PIM-based platforms when processing numeric data sets.ReCSA also has 24.82×,32.94×,and 18.22×performance improvement when processing string data sets compared with CPU-,GPU-,and FPGA-based platforms.

PRAP-PIM:A weight pattern reusing aware pruning method for ReRAM-based PIM DNN accelerators

Resistive Random-Access Memory(ReRAM)based Processing-in-Memory(PIM)frameworks are proposed to accelerate the working process of DNN models by eliminating the data movement between the computing and memory units.To further mitigate the space and energy consumption,DNN model weight sparsity and weight pattern repetition are exploited to optimize these ReRAM-based accelerators.However,most of these works only focus on one aspect of this software/hardware codesign framework and optimize them individually,which makes the design far from optimal.In this paper,we propose PRAP-PIM,which jointly exploits the weight sparsity and weight pattern repetition by using a weight pattern reusing aware pruning method.By relaxing the weight pattern reusing precondition,we propose a similarity-based weight pattern reusing method that can achieve a higher weight pattern reusing ratio.Experimental results show that PRAP-PIM achieves 1.64×performance improvement and 1.51×energy efficiency improvement in popular deep learning benchmarks,compared with the state-of-the-art ReRAM-based DNN accelerators.