Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

基于Python脚本的SoC寄存器模块自动化设计

片上系统芯片(SoC)包含大量可通过系统总线配置的寄存器模块。在芯片设计流程中,需要人工设计寄存器模块功能,并形成可阅读的设计文档,再由硬件描述语言(Hardware Description Language)描述为实际数字电路,还需要有便于芯片仿真验证的寄存器模型以及基于C语言的嵌入式固件程序用于应用软件开发。本文提供一种基于Python脚本语言的芯片设计流程,将上述芯片设计流程串联起来,做到一次规格设计,自动化输出寄存器模块的不同设计描述,有效提高了SoC芯片设计效率。

Tire Pressure Monitoring System Using SoC and Low Power Design

This paper presents the tire pressure monitoring system (TPMS) by using the system on chip (SoC) mixed signals with the help of Bluetooth transmission and in advantage of low power consumption design. This is to monitor the variations in temperature and pressure of the vehicle’s tire, and the TPMS system is involved. It improves the driver’s safety by automatically detecting the tire pressure and temperature and then warning signal is sent to driver to take a measure, which prevents from accident. The proposed system of tire pressure monitoring system using SoC increases the speed of indication time to the driver by using mixed signals. The inflation of the tire can be avoided by preventing from high temperature and high pressure. Limitation of temperature and pressure in the previous system is also elongated i.e. temperature from 40℃ to 125℃ and pressure from 0 to 750 Kpa. Sensors, wireless communication (Bluetooth dongle) and SoC unit are used to design the low power TPMS. Quantitative results are taken and the analogy between temperature and pressure is also verified. The tested results proved by need of the practical system. Signal conditioning voltage and SoC unit is the trace for low power design TPMS. Finally, the performance of the system is tested and executed by using proteus software given as a real time application.

Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip

As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively.

基于SystemC的SoC行为级软硬件协同设计

针对目前SoC设计中存在的软硬件协同验证的时间瓶颈问题,提出了一种使用系统建模语言SystemC对SoC进行总线周期精确行为级建模的方法,采用该方法构建SoC芯片总线周期精确行为级模型进行前期验证。该模型基于32位RISC构建,并可配置其它硬件模块。实验结果表明:模型完全仿真实际硬件电路,所有的接口信号在系统时钟的任一时刻被监测和分析,很大程度地提高了仿真速度,并且可以在前期作系统的软硬件协同仿真和验证,有效地缩短了目前SoC芯片设计中在RTL级作软硬件协同仿真验证时的时间开销。

SoC设计中WISHBONE片上总线的设计与开发

讨论了 WISHBONE片上总线的主要实现技术及其在 So C可重用设计中的主要作用 ,以及 WISHBONE体系结构在 So C中的应用 ,并以 EPStar1嵌入式微处理器中WISHBONE的设计与实现为例 ,说明了采用 WISHBONE片上总线实现 So C可重用设计的方法。

基于Petri网和systemC的SoC系统描述

针对Petri网自带信息不足、硬件描述能力弱以及systemC无可视性等缺陷,将Petri网与systemC相结合来进行系统级建模。通过分析Petri网和systemC的相似点,建立Petri网和systemC的映射关系,以便于将Petri网描述的系统模型转化为systemC代码。同时,使用层次建模的方法防止状态爆炸。通过以上方式建立系统级模型,描述片上系统(SoC)嵌入式系统软硬件状态,作为可执行的系统级描述。

LOGIC STRUCTURE OF PROGRAMMABLE INSTRUCTIONS FOR JAVA PROCESSORS

There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.

The Design of PSM-Based ECRH Power Supply Control System

Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhile adds the difficulty of designing and building the control system of its power source. In this paper, the method of designing a control system based on Single Chip Microcomputer (SCM) and Field Programmable Gate Array (FPGA) is introduced according to its main requirements. The experimental results show that the control system in this paper achieves the conversion of different working modes, gets exact timing, and realizes the failure protection in 10us thus can be used in the ECRH system.

Stepping Control Method of Linear Displacement Mechanism Driven by TRUM Based on PSoC

A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.

Signal processing for PSoC based PIR motion detection

A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.

基于SiliconBackPlane平台的机顶盒soc设计（英文）

随着IC技术的发展,利用IP库为机顶盒芯片提供了一个完美的解决方案。单片soc相比以前的芯片组解决方案具有很多直接的优势,比如能耗和面积。该文尝试利用SiliconBackPlane平台来设计了一种机顶盒的soc。首先,建立了机顶盒soc体系的数据流图,进行了系统划分,诸如,CPU,DSP,存储单元及其他的一些数字模块。然后,利用SiliconBackPlane平台完成soc的片上总线设计,以适应不同模块的通信带宽。最后,进行了简短的分析。

Research on object-oriented SOC design methodology

The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There are many practical problems in the application of object-oriented methods for this goal. Based on the analysis of traditional and system-level design methodology, a new object-oriented SOC design methodology with object-oriented design patterns is proposed, which emphasizes high-level design and verification. Aiming at the final goal of developing design patterns specific to SOC design, the reuse of design patterns in SOC systems and the capability of new SOC design patterns are discussed. With the illustration of some concrete examples of SOC design patterns, the application of object-oriented design methodology in the SOC design process is presented.

Designing cost-effective network-on-chip by dual-channel access mechanism

A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.

Novel Asynchronous Wrapper and Its Application to GALS Systems

An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous （GALS） systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Mttller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.

CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION

The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.

基于RISC-V架构的行人定位SoC系统设计

行人定位方法中,捷联式惯导定位系统需要处理惯性测量单元(IMU)传感器的数据,通过算法处理后得到行人的位置,因此对于芯片实时性以及低功耗有很高的要求。由于行人定位算法大多基于浮点传感器数据开发,一般要求终端设备能够处理浮点数据。第五代精简指令集(RISC-V)架构作为一种开源架构,能节约架构授权费,在物联网领域有着广泛应用,并且其浮点(F)和向量(V)等高性能扩展指令能够很好地满足行人定位算法对实时性的要求。针对行人定位系统的特定性能要求,提出了一种基于浮点内核向量处理器优化RISC-V架构的行人定位片上系统(SoC),并在实际系统中进行验证。与多个准32位架构RISC-V处理器以及高层次综合组件(HLS)生成的算法专用IP(locate_IP)的标准处理器方案的性能对比分析表明,该设计实现了34倍的性能提升以及5.6倍的能效提升,满足了微终端的要求。

基于SoC的非对称数字系统算法设计与实现

文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。

Design and Implementation of Single Chip WCDMA High Speed Channel Decoder

A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.