The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the p...The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.展开更多
To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip:Programmable System on Chip (PSoC) and through chronic electrodes in the c...To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip:Programmable System on Chip (PSoC) and through chronic electrodes in the cortex. With PSoC family member CY8C29466,the system completed operational and instrument amplifiers, filters, timers, AD convertors, and serial communication, etc. The signal processing was dealt with virtual instrument technology. All of these factors can significantly affect the price and development cycle of the project. The result showed that the system was able to record and analyze neural extrocellular discharge generated by neurons continuously for a week or more. This is very useful for the interdisciplinary research of neuroscience and information engineering technique. The circuits and architecture of the devices can be adapted for neurobiology and research with other small animals.展开更多
SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programm...SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.展开更多
The design of iterative learning controller(ILC) requires to store the system input, output or control parameters of previous trials for generating the input of the current trial. In order to apply the iterative learn...The design of iterative learning controller(ILC) requires to store the system input, output or control parameters of previous trials for generating the input of the current trial. In order to apply the iterative learning controller for a real application and reduce the memory size for implementation, a current error based sampled-data proportional-derivative(PD) type iterative learning controller is proposed for control systems with initial resetting error, input disturbance and output measurement noise in this paper.The proposed iterative learning controller is simple and effective. The first contribution in this paper is to prove the learning error convergence via a rigorous technical analysis. It is shown that the learning error will converge to a residual set if a forgetting factor is introduced in the controller. All the theoretical results are also shown by computer simulations. The second main contribution is to realize the iterative learning controller by a digital circuit using a field programmable gate array(FPGA) chip applied to repetitive position tracking control of direct current(DC) motors. The feasibility and effectiveness of the proposed current error based sampleddata iterative learning controller are demonstrated by the experiment results. Finally, the relationship between learning performance and design parameters are also discussed extensively.展开更多
基金supported by National Key Basic Research Program of China(973 ProgramGrant No.2011CB706804)+1 种基金Shanghai Municipal Science and Technology Commission of China(Grant No.11QH1401400)Research Project of State Key Laboratory of Mechanical System & Vibration of China(Grant No.MSVMS201102)
文摘The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.
基金Shandong Province Nature Science FoundationGrant number:Y2007C02+1 种基金Science Development PlanGrant number:2006GG3204006
文摘To collect neural activity data from awake, behaving freely animals, we develop miniaturized implantable recording system by the modem chip:Programmable System on Chip (PSoC) and through chronic electrodes in the cortex. With PSoC family member CY8C29466,the system completed operational and instrument amplifiers, filters, timers, AD convertors, and serial communication, etc. The signal processing was dealt with virtual instrument technology. All of these factors can significantly affect the price and development cycle of the project. The result showed that the system was able to record and analyze neural extrocellular discharge generated by neurons continuously for a week or more. This is very useful for the interdisciplinary research of neuroscience and information engineering technique. The circuits and architecture of the devices can be adapted for neurobiology and research with other small animals.
基金supported by the Major Special Projects on National Medium and Long-term Science and Technology Development Planning
文摘SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.
基金supported by National Science Council,Taiwan,China(No.NSC102-2221-E-211-011)National Nature Science Foundation of China(No.61374102)
文摘The design of iterative learning controller(ILC) requires to store the system input, output or control parameters of previous trials for generating the input of the current trial. In order to apply the iterative learning controller for a real application and reduce the memory size for implementation, a current error based sampled-data proportional-derivative(PD) type iterative learning controller is proposed for control systems with initial resetting error, input disturbance and output measurement noise in this paper.The proposed iterative learning controller is simple and effective. The first contribution in this paper is to prove the learning error convergence via a rigorous technical analysis. It is shown that the learning error will converge to a residual set if a forgetting factor is introduced in the controller. All the theoretical results are also shown by computer simulations. The second main contribution is to realize the iterative learning controller by a digital circuit using a field programmable gate array(FPGA) chip applied to repetitive position tracking control of direct current(DC) motors. The feasibility and effectiveness of the proposed current error based sampleddata iterative learning controller are demonstrated by the experiment results. Finally, the relationship between learning performance and design parameters are also discussed extensively.