Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic...Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.展开更多
A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device....A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.展开更多
基金supported by the National Natural Science Foundation of China(61401204)the Fundamental Research Funds for the Central Universities(30916011319)+1 种基金the Technology Research and Development Program of Jiangsu Province(BY2015004-03)the Postdoctoral Science Foundation of Jiangsu Province(1501104C)
文摘Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.
基金Supported by the National High Technology Research and Development Program(No.2012AA121901)
文摘A kind of architecture of Time-to-Digital Converter(TDC) for Ultra-WideBand(UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array(FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines(PDLs) or a two-channel PDL. One line(channel) delays the rising edge and the other line(channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%–1.60%.
