A novel programmable gain amplifier( PGA) based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers( VGA),a binary-weighted switching technique is employed...A novel programmable gain amplifier( PGA) based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers( VGA),a binary-weighted switching technique is employed to vary the current-steering transistors' aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature( PVT). P-well NMOS( Nmetal oxide semiconductor) transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS( complementary metal oxide semiconductor)process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point(OIP3) and minimum noise figure( NF) are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.展开更多
A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides ...A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.展开更多
A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A tw...A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.展开更多
A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorde...A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.展开更多
A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and e...A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.展开更多
A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a curren...A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 #m CMOS process. Tests show that it achieves an IIP3 (third-order intercept point) of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of-36.2 to 23.5 dB with a resolution of 0.32 dB.展开更多
This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibrat...This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.展开更多
This paper presents a VHF(30-300 MHz) RF programmable gain amplifier(PGA) with an adaptive phase correction technique.The proposed technique effectively mitigates phase errors over the VHF band,and the RFPGA as a ...This paper presents a VHF(30-300 MHz) RF programmable gain amplifier(PGA) with an adaptive phase correction technique.The proposed technique effectively mitigates phase errors over the VHF band,and the RFPGA as a whole satisfies all the specifications of the China mobile multimedia broadcasting VHF band applications.The RFPGA is implemented with a TSMC 0.25μm CMOS process.Measurement results reveal a gain range of around 61 dB,an ⅡP3 of-7 dBm at maximum gain,a power consumption of 10.2 mA at maximum gain,and a phase imbalance of less than 0.3 degrees.展开更多
This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier(PGA).The PGA consists of three-stage amplifiers, which includes...This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier(PGA).The PGA consists of three-stage amplifiers, which includes a variable gain amplifier and DC offset cancellation circuits.The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz.The chip was fabricated in 0.13μm CMOS technology. Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB.At the gain setting of 60 dB,the bandwidth can be tuned from 1 to 10 MHz,while the power consumption can be programmed from 850μA to 3.2 mA at a supply voltage of 1.2 V.Its in-band OIP3 result is at 14 dBm.展开更多
A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlat...A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlated double sampler(CDS) with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion(SNDR) is 70.3 dB,the effective number of bits is 11.39 bit.展开更多
基金The National Natural Science Foundation of China(No.61306069)
文摘A novel programmable gain amplifier( PGA) based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers( VGA),a binary-weighted switching technique is employed to vary the current-steering transistors' aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature( PVT). P-well NMOS( Nmetal oxide semiconductor) transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS( complementary metal oxide semiconductor)process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point(OIP3) and minimum noise figure( NF) are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.
基金Project supported by the National Natural Science Foundation of China(Nos.61106024,61201176)
文摘A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.
文摘A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.
基金supported by the National Basic Research Program of China(No.2011CB933203)the National Natural Science Foundation of China(Nos.61076023,61178051)the National High Technology Research & Development Program of China(No.2012AA030608)
文摘A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4thorder Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 μS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.
基金supported by the National Natural Science Foundation of China (No. 60576025)the Tianjin Innovation Special Funds forScience and Technology, China (No. 05FZZDGX00200).
文摘A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.
基金supported by the National High-Tech R&D Program of China(No.2011AA040102)the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2009ZX01031-002-008-002)
文摘A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 #m CMOS process. Tests show that it achieves an IIP3 (third-order intercept point) of -17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of-36.2 to 23.5 dB with a resolution of 0.32 dB.
基金Project supported by the Provincial and Ministerial Industry-Academia Cooperation Project of China(No.2009A090100019)
文摘This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.
文摘This paper presents a VHF(30-300 MHz) RF programmable gain amplifier(PGA) with an adaptive phase correction technique.The proposed technique effectively mitigates phase errors over the VHF band,and the RFPGA as a whole satisfies all the specifications of the China mobile multimedia broadcasting VHF band applications.The RFPGA is implemented with a TSMC 0.25μm CMOS process.Measurement results reveal a gain range of around 61 dB,an ⅡP3 of-7 dBm at maximum gain,a power consumption of 10.2 mA at maximum gain,and a phase imbalance of less than 0.3 degrees.
基金Project supported by the National High-Tech Research and Development Program of China(No.2009AA011606)the National Natural Science Foundation of China(No.60976023)
文摘This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier(PGA).The PGA consists of three-stage amplifiers, which includes a variable gain amplifier and DC offset cancellation circuits.The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz.The chip was fabricated in 0.13μm CMOS technology. Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB.At the gain setting of 60 dB,the bandwidth can be tuned from 1 to 10 MHz,while the power consumption can be programmed from 850μA to 3.2 mA at a supply voltage of 1.2 V.Its in-band OIP3 result is at 14 dBm.
基金supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033)the National High-Tech Program of China (No. 2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302)
文摘A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlated double sampler(CDS) with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion(SNDR) is 70.3 dB,the effective number of bits is 11.39 bit.