Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

RKDG Methods with Multi-resolution WENO Limiters for Solving Steady-State Problems on Triangular Meshes

In this paper, we design high-order Runge-Kutta discontinuous Galerkin (RKDG) methods with multi-resolution weighted essentially non-oscillatory (multi-resolution WENO) limiters to compute compressible steady-state problems on triangular meshes. A troubled cell indicator extended from structured meshes to unstructured meshes is constructed to identify triangular cells in which the application of the limiting procedures is required. In such troubled cells, the multi-resolution WENO limiting methods are used to the hierarchical L^(2) projection polynomial sequence of the DG solution. Through using the RKDG methods with multi-resolution WENO limiters, the optimal high-order accuracy can be gradually reduced to first-order in the triangular troubled cells, so that the shock wave oscillations can be well suppressed. In steady-state simulations on triangular meshes, the numerical residual converges to near machine zero. The proposed spatial reconstruction methods enhance the robustness of classical DG methods on triangular meshes. The good results of these RKDG methods with multi-resolution WENO limiters are verified by a series of two-dimensional steady-state problems.

Reconfigurable mechanism-based metamaterials for ternary-coded elastic wave polarizers and programmable refraction control

Elastic metamaterials with unusual elastic properties offer unprecedented ways to modulate the polarization and propagation of elastic waves.However,most of them rely on the resonant structural components,and thus are frequency-dependent and unchangeable.Here,we present a reconfigurable 2D mechanism-based metamaterial which possesses transformable and frequency-independent elastic properties.Based on the proposed mechanism-based metamaterial,interesting functionalities,such as ternarycoded elastic wave polarizer and programmable refraction,are demonstrated.Particularly,unique ternary-coded polarizers,with 1-trit polarization filtering and 2-trit polarization separating of longitudinal and transverse waves,are first achieved.Then,the strong anisotropy of the proposed metamaterial is harnessed to realize positive-negative bi-refraction,only-positive refraction,and only-negative refraction.Finally,the wave functions with detailed microstructures are numerically verified.

Wavelet Multi-Resolution Interpolation Galerkin Method for Linear Singularly Perturbed Boundary Value Problems

In this study,a wavelet multi-resolution interpolation Galerkin method(WMIGM)is proposed to solve linear singularly perturbed boundary value problems.Unlike conventional wavelet schemes,the proposed algorithm can be readily extended to special node generation techniques,such as the Shishkin node.Such a wavelet method allows a high degree of local refinement of the nodal distribution to efficiently capture localized steep gradients.All the shape functions possess the Kronecker delta property,making the imposition of boundary conditions as easy as that in the finite element method.Four numerical examples are studied to demonstrate the validity and accuracy of the proposedwavelet method.The results showthat the use ofmodified Shishkin nodes can significantly reduce numerical oscillation near the boundary layer.Compared with many other methods,the proposed method possesses satisfactory accuracy and efficiency.The theoretical and numerical results demonstrate that the order of theε-uniform convergence of this wavelet method can reach 5.

A novel one-time-programmable memory unit based on Schottky-type p-GaN diode

In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.

Teaching Reform and Exploration of Practical Courses Based on Programmable Control

As the country continues to promote the development of intelligent manufacturing,all industries are carrying out enterprise automation upgrading,the Pearl River Delta Intelligent Manufacturing Conference held in March 2024 provides a direction guide for each enterprise on how to integrate the intelligent manufacturing technology into each link and provide direction guidance for enterprises to create new models and new business formats.College teachers,in focusing on the teaching process,should closely match the enterprise and social needs and cultivate excellent students.As the core controller of automation control,the application of programmable controllers in teaching is particularly important.In practical classes,by setting progressive difficulty,project guidance,team collaboration,and other links,students can master the automation equipment design of programmable control in repeated practice.

Low-loss chip-scale programmable silicon photonic processor

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility,and thus makes it possible to develop large-scale programmable optical signal processors.The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors.In this paper,we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches.The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers(MZCs),four Ge/Si photodetectors,four channels of thermally-tunable optical delaylines.Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step.Particularly,these waveguide spirals used here are designed to be as wide as 2μm,enabling an ultralow propagation loss of 0.28 dB/cm.Meanwhile,these MZCs and MZSs are designed with 2-μm-wide arm waveguides,and thus the random phase errors in the MZC/MZS arms are negligible,in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly.Finally,this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities,including tunable time-delay,microwave photonic beamforming,arbitrary optical signal filtering,and arbitrary waveform generation.

Programmable Logic Controller Block Monitoring System for Memory Attack Defense in Industrial Control Systems

Cyberattacks targeting industrial control systems(ICS)are becoming more sophisticated and advanced than in the past.A programmable logic controller(PLC),a core component of ICS,controls and monitors sensors and actuators in the field.However,PLC has memory attack threats such as program injection and manipulation,which has long been a major target for attackers,and it is important to detect these attacks for ICS security.To detect PLC memory attacks,a security system is required to acquire and monitor PLC memory directly.In addition,the performance impact of the security system on the PLC makes it difficult to apply to the ICS.To address these challenges,this paper proposes a system to detect PLC memory attacks by continuously acquiring and monitoring PLC memory.The proposed system detects PLC memory attacks by acquiring the program blocks and block information directly from the same layer as the PLC and then comparing them in bytes with previous data.Experiments with Siemens S7-300 and S7-400 PLC were conducted to evaluate the PLC memory detection performance and performance impact on PLC.The experimental results demonstrate that the proposed system detects all malicious organization block(OB)injection and data block(DB)manipulation,and the increment of PLC cycle time,the impact on PLC performance,was less than 1 ms.The proposed system detects PLC memory attacks with a simpler detection method than earlier studies.Furthermore,the proposed system can be applied to ICS with a small performance impact on PLC.

Recognition of Hybrid PQ Disturbances Based on Multi-Resolution S-Transform and Decision Tree

Aiming at the problems of multiple types of power quality composite disturbances,strong feature correlation and high recognition error rate,a method of power quality composite disturbances identification based on multiresolution S-transform and decision tree was proposed.Firstly,according to IEEE standard,the signal models of seven single power quality disturbances and 17 combined power quality disturbances are given,and the disturbance waveform samples are generated in batches.Then,in order to improve the recognition accuracy,the adjustment factor is introduced to obtain the controllable time-frequency resolution through multi-resolution S-transform time-frequency domain analysis.On this basis,five disturbance time-frequency domain features are extracted,which quantitatively reflect the characteristics of the analyzed power quality disturbance signal,which is less than the traditional method based on S-transform.Finally,three classifiers such as K-nearest neighbor,support vector machine and decision tree algorithm are used to effectively complete the identification of power quality composite disturbances.Simulation results showthat the classification accuracy of decision tree algorithmis higher than that of K-nearest neighbor and support vector machine.Finally,the proposed method is compared with other commonly used recognition algorithms.Experimental results show that the proposedmethod is effective in terms of detection accuracy,especially for combined PQ interference.

High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

Efficient Sparse-Grid Implementation of a Fifth-Order Multi-resolution WENO Scheme for Hyperbolic Equations

High-order accurate weighted essentially non-oscillatory(WENO)schemes are a class of broadly applied numerical methods for solving hyperbolic partial differential equations(PDEs).Due to highly nonlinear property of the WENO algorithm,large amount of computational costs are required for solving multidimensional problems.In our previous work(Lu et al.in Pure Appl Math Q 14:57–86,2018;Zhu and Zhang in J Sci Comput 87:44,2021),sparse-grid techniques were applied to the classical finite difference WENO schemes in solving multidimensional hyperbolic equations,and it was shown that significant CPU times were saved,while both accuracy and stability of the classical WENO schemes were maintained for computations on sparse grids.In this technical note,we apply the approach to recently developed finite difference multi-resolution WENO scheme specifically the fifth-order scheme,which has very interesting properties such as its simplicity in linear weights’construction over a classical WENO scheme.Numerical experiments on solving high dimensional hyperbolic equations including Vlasov based kinetic problems are performed to demonstrate that the sparse-grid computations achieve large savings of CPU times,and at the same time preserve comparable accuracy and resolution with those on corresponding regular single grids.

National Social Investment Programmes in Nigeria:A Descriptive Analysis of the Socio-Economic Contributions of N-Power Programme in Benue State

This study analysed the socio-economic contributions of N-Power programme amongst the beneficiaries of the scheme in Benue State.Prior to the introduction of N-Power programme,successive administrations in Nigeria have made concerted efforts towards improving the standard of living of the citizenry through the execution of various welfare or social intervention programmes,but not much successes were recorded.Learning from the mistakes of the past regimes,and by way of deliberate state policy,the Buhari’s government initiated a multi-pronged social investment policy,one of which is the N-power programme that came onboard in 2016,which also doubles as the subject of this study.To achieve the goal of this study,a combination of desktop research and survey design was employed.Questionnaires were administered to 390 respondents through a combination of stratified and random sampling techniques.The results of the survey were matched with that of the secondary data obtained through online websites and other related sources.The result indicated that N-Power made positive contributions to the socio-economic life of the beneficiaries in Benue State:specifically,the scheme contributed in poverty eradication,employment generation,skills acquisitions and capacity building.However,some aspect of our findings revealed that the programme has a number of challenges such as:inadequate cash support,delay in monthly cash transfer to beneficiaries,distance participants had to move to their work stations,absence of posting in N-Teach scheme,and lack of adequate working tools amongst others.To salvage this problem the paper recommended the following solutions:expansion of the scheme to cover N-Teach and other aspects,increment in the monthly cash transfer to cushion the high rate of inflation,support for the participants/beneficiaries in transportation and logistics,enrolment of more youth into the various schemes,proper monitoring and evaluation of the implementation of the schemes amongst others.

一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

IC Implementation of a Programmable CMOS Voltage Reference

A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.

Multi-resolution graph-based clustering analysis for lithofacies identifi cation from well log data: Case study of intraplatform bank gas fi elds, Amu Darya Basin

In this study, we used the multi-resolution graph-based clustering （MRGC） method for determining the electrofacies （EF） and lithofacies （LF） from well log data obtained from the intraplatform bank gas fields located in the Amu Darya Basin. The MRGC could automatically determine the optimal number of clusters without prior knowledge about the structure or cluster numbers of the analyzed data set and allowed the users to control the level of detail actually needed to define the EF. Based on the LF identification and successful EF calibration using core data, an MRGC EF partition model including five clusters and a quantitative LF interpretation chart were constructed. The EF clusters 1 to 5 were interpreted as lagoon, anhydrite flat, interbank, low-energy bank, and high-energy bank, and the coincidence rate in the cored interval could reach 85%. We concluded that the MRGC could be accurately applied to predict the LF in non-cored but logged wells. Therefore, continuous EF clusters were partitioned and corresponding LF were characteristics ＆different LF were analyzed interpreted, and the distribution and petrophysical in the framework of sequence stratigraphy.

Multi-resolution image segmentation based on Gaussian mixture model

Mixture model based image segmentation method, which assumes that image pixels are independent and do not consider the position relationship between pixels, is not robust to noise and usually leads to misclassification. A new segmentation method, called multi-resolution Ganssian mixture model method, is proposed. First, an image pyramid is constructed and son-father link relationship is built between each level of pyramid. Then the mixture model segmentation method is applied to the top level. The segmentation result on the top level is passed top-down to the bottom level according to the son-father link relationship between levels. The proposed method considers not only local but also global information of image, it overcomes the effect of noise and can obtain better segmentation result. Experimental result demonstrates its effectiveness.

Winter wheat identification by integrating spectral and temporal information derived from multi-resolution remote sensing data

Timely crop acreage and distribution information are the basic data which drive many agriculture related applications.For identifying crop types based on remote sensing,methods using only a single image type have significant limitations.Current research that integrates fine and coarser spatial resolution images,using techniques such as unmixing methods,regression models,and others,usually results in coarse resolution abundance without sufficient detail within pixels,and limited attention has been paid to the spatial relationship between the pixels from these two kinds of images.Here we propose a new solution to identify winter wheat by integrating spectral and temporal information derived from multi-resolution remote sensing data and determine the spatial distribution of sub-pixels within the coarse resolution pixels.Firstly,the membership of pixels which belong to winter wheat is calculated using a 25-m resolution resampled Landsat Thematic Mapper(TM)image based on the Bayesian equation.Then,the winter wheat abundance(acreage fraction in a pixel)is assessed by using a multiple regression model based on the unique temporal change features from moderate resolution imaging spectroradiometer(MODIS)time series data.Finally,winter wheat is identified by the proposed Abundance-Membership(AM)model based on the spatial relationship between the two types of pixels.Specifically,winter wheat is identified by comparing the spatially corresponding 10×10 membership pixels of each abundance pixel.In other words,this method takes advantage of the relative size of membership in a local space,rather than the absolute size in the entire study area.This method is tested in the major agricultural area of Yiluo Basin,China,and the results show that acreage accuracy(Aa)is 93.01%and sampling accuracy(As)is 91.40%.Confusion matrix shows that overall accuracy(OA)is 91.4%and the kappa coefficient(Kappa)is 0.755.These values are significantly improved compared to the traditional Maximum Likelihood classification(MLC)and Random Forest classification(RFC)which rely on spectral features.The results demonstrate that the identification accuracy can be improved by integrating spectral and temporal information.Since the identification of winter wheat is performed in the space corresponding to each MODIS pixel,the influence of differences of environmental conditions is greatly reduced.This advantage allows the proposed method to be effectively applied in other places.

A signal-summing programmable gain amplifier employing binary-weighted switching and constant-g--_m bias

A novel programmable gain amplifier（ PGA） based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers（ VGA）,a binary-weighted switching technique is employed to vary the current-steering transistors＇ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6dB is achieved. The constant-g_m biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature（ PVT）. P-well NMOS（ Nmetal oxide semiconductor） transistors are utilized to eliminate the influence of back-gate effect which will induce gain error.The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a0.18 μm CMOS（ complementary metal oxide semiconductor）process. The measurement results show a variable gain ranging from 0 to24 dB with a step size of 6 dB and a maximum gain error of 0. 3dB. A constant 3dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point（OIP3） and minimum noise figure（ NF） are20. 9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm^2. The total power consumption is4. 8 mW under a 1. 8 V supply voltage.