ASIC Design and Implementation for Digital Pulse Compression Chip

A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

A Reconfigurable Instrument System for Nuclear and Particle Physics Experiments

We developed a reconfigurable nuclear instrument system （RNIS） that could satisfy the requirements of diverse nuclear and particle physics experiments, and the inertial confinement fusion diagnostic. Benefiting from the reconfigurable hardware structure and digital pulse processing technology RNIS shakes off the restrictions of cumbersome crates and miscellaneous modules. It retains all the advantages of conventional nuclear instruments and is more flexible and portable. RNIS is primarily composed of a field programmable hardware board and relevant t）C software. Separate analog channels are designed to provide different functions, such as am- plifiers, ADC, fast discriminators and Schmitt discriminators for diverse experimental purposes. The high-perfornmnce field programnmble gate array could complete high-precision time interval measurement, histogram accumulation, counting, and coincidence anticoincidence measurement. To illustrate tile prospects of RNIS, a series of applications to the experiments are described in this paper. The first, for which RNIS was originally developed, involves nuclear energy spectrum mea- surement with a scintillation detector and photonmltiplier. The second experiment applies RNIS to a G-M tube counting experiment, and in tile third, it is applied to a quantum comnnmication experiment tllrough reconfiguration.

A Protocol for Digitalized Collection of Traditional Chinese Medicine(TCM)Pulse Information Using Bionic Pulse Diagnosis Equipment

Pulse diagnosis equipment used in Traditional Chinese Medicine(TCM)has long been developed for collecting pulse information and in TCM research.However,it is still difficult to implement pulse taking automatically or efficiently in clinical practice.Here,we present a digital protocol for TCM pulse information collection based on bionic pulse diagnosis equipment,which ensures high efficiency,reliability and data integrity of pulse diagnosis information.A four-degree-of-freedom pulse taking platform together with a wrist bracket can satisfy the spatial positioning and angle requirements for individually adaptive pulse acquisition.Three-dimensional reconstruction of a wrist surface and an image localization model are combined to provide coordinates of the acquisition position and detection direction automatically.Three series elastic joints can not only simulate the TCM pulse taking method that“Three fingers in a straight line,the middle finger determining the‘Guan’location and finger pulp pressing on the radial artery,”but also simultaneously carry out the force-controlled multi-gradient pressing process.In terms of pulse information integrity,this proposed protocol can generate rich pulse information,including basic individual information,pulse localization distribution,multi-gradient dynamic pulse force time series,and objective pulse parameters,which can help establish the fundamental data sets that are required as the pulse phenotype for subsequent comprehensive analysis of pulse diagnosis.The implementation of this scheme is beneficial to promote the standardization of the digitalized collection of pulse information,the effectiveness of detecting abnormal health status,and the promotion of the fundamental and clinical research of TCM,such as TCM pulse phenomics.

Dwell Scheduling Algorithm for Digital Array Radar

Aiming at the problem of resource allocation for digital array radar（ DAR）,a dwell scheduling algorithm is proposed in this paper. Firstly,the integrated priority of different radar tasks is designed,which ensures that the imaging tasks are scheduled without affecting the search and tracking tasks; Then,the optimal scheduling model of radar resource is established according to the constraints of pulse interleaving; Finally,a heuristic algorithm is used to solve the problem and a sparse-aperture cognitive ISAR imaging method is used to achieve partial precision tracking target imaging. Simulation results demonstrate that the proposed algorithm can both improve the performance of the radar system,and generate satisfactory imaging results.

Digital pulse deconvolution method for current tails of NaI(Tl) detectors

To overcome the problem of pulse pile-up at high count rates, a digital deconvolution algorithm is used to remove the exponential current tails of NaI（Tl） detectors, so as to obtain a current unit impulse. Then a narrow pulse can be obtained through pulse shaping. The pulse deconvolution technique can thoroughly eliminate the influences of ballistic deficit and improve traditional pulse shaping systems in both pulse throughput and energy resolution. To demonstrate this method, the energy spectrum of a ^137Cs radioactive source was measured. When the shaping time constant is 1.5 μs, traditional pulse shaping systems yielded a 6.99% energy resolution and 68 kcps count rate, while the new pulse deconvolution technique, used to improve traditional pulse shaping systems, yielded a 6.37% energy resolution and 102 kcps count rate.

3D visualization using pulsed and CW digital holographic tomography techniques

We outline the use of digital holographic tomography to determine the three-dimensional （3D） shapes of falling and static objects, such as lenslets and water droplets. Reconstruction of digitally recorded inline holograms is performed using multiplicative and Radon transform techniques to reveal the exact 3D shapes of the objects.