主要阐述了电荷泵技术在14 V HV MOS晶体管可靠性研究中的应用。使用了一种改进的电荷泵技术分析了经过热载流子加压后的器件特性。使用这种方法,我们可以精确描述器件损伤的位置和程度,以及可以精确评估由于HCI效应引起的界面缺陷的变...主要阐述了电荷泵技术在14 V HV MOS晶体管可靠性研究中的应用。使用了一种改进的电荷泵技术分析了经过热载流子加压后的器件特性。使用这种方法,我们可以精确描述器件损伤的位置和程度,以及可以精确评估由于HCI效应引起的界面缺陷的变化,为器件优化与工艺改进提供重要参考信息。展开更多
Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed...Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed results show that the D peak in DCIV spectrum,which related to the drain region,is affected by a superfluous drain leakage current.The band trap band tunneling current is dominant of this current.展开更多
A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with r...A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.展开更多
A diagram representation method is proposed to interpret the complicated charge pumping（CP） processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence,...A diagram representation method is proposed to interpret the complicated charge pumping（CP） processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence, frequency dependence,the voltage dependence for the fast and slow traps,and the geometric CP component are clearly illustrated at a glance by the diagram representation.For the slow trap CP measurement,there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture,and the CP current is determined by the lower capturing electron or hole component.The method is used to discuss the legitimacy of the newly developed modified charge pumping method.展开更多
文摘Interface traps generated under hot carrier (HC) stress in LDD nMOST's are monitored by the direct current current voltage (DCIV) measurement technique and charge pumping (CP) technique.The measured and analyzed results show that the D peak in DCIV spectrum,which related to the drain region,is affected by a superfluous drain leakage current.The band trap band tunneling current is dominant of this current.
基金Project supported by the National Natural Science Foundation of China(No.61376031)。
文摘A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.
基金Project supported by the Micro/Nano-Electronics Science and Technology Innovation Platform of Fudan University,National Natural Science Foundation of China(No.60936005)the National VLSI Project(No.2009ZX02035-003).
文摘A diagram representation method is proposed to interpret the complicated charge pumping（CP） processes. The fast and slow traps in CP measurement are defined.Some phenomena such as CP pulse rise/fall time dependence, frequency dependence,the voltage dependence for the fast and slow traps,and the geometric CP component are clearly illustrated at a glance by the diagram representation.For the slow trap CP measurement,there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture,and the CP current is determined by the lower capturing electron or hole component.The method is used to discuss the legitimacy of the newly developed modified charge pumping method.
