DESIGN OF QUASI-CYCLIC LDPC CODES BASED ON EUCLIDEAN GEOMETRIES

A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.

Combinatorial design-based quasi-cyclic LDPC codes with girth eight

This paper presents a novel regular Quasi-Cyclic (QC)Low Density Parity Check (LDPC)codes with columnweight three and girth at least eight.These are designed on the basis of combinatorial design in which subsets applied for the construction of circulant matrices are determined by a particular subset.Considering the nonexistence of cycles four and six in the structure of the parity check matrix,a bound for their minimum weight is proposed.The simtdations conducted confirm that without applying a masking technique,the newly implemented codes have a performance similar to or better than other well-known codes.This is evident in the waterfall region, while their error floor at very low Bit Error Rate (BER)is expected.

On the Girth of Tanner (5,7) Quasi-Cyclic LDPC Codes

The girth plays an important role in the design of LDPC codes. In order to determine the girth of Tanner(5,7) quasi-cyclic( QC) LDPC codes with length 7p for p being a prime with the form 35 m + 1,the cycles of lengths 4,6,8,and 10 are analyzed. Then these cycles are classified into sixteen categories,each of which can be expressed as an ordered block sequence,or a certain type. It is also shown that the existence of these cycles is equal to polynomial equations over Fpwho has a 35th unit root. We check if these polynomial equations have a 35th unit root and obtain the girth values of Tanner(5,7) QC LDPC codes.

Quasi-cyclic LDPC codes with high-rate and low error floor based on Euclidean geometries

An improved Euclidean geometry approach to design quasi-cyclic （QC） Low-density parity-check （LDPC） codes with high-rate and low error floor is presented. The constructed QC-LDPC codes with high-rate have lower error floor than the original codes. The distribution of the minimum weight codeword is analyzed, and a sufficient existence condition of the minimum weight codeword is found. Simulations show that a lot of QC-LDPC codes with lower error floor can be designed by reducing the number of the minimum weight codewords satisfying this sufficient condition.

Design and Efficient Hardware Implementation Schemes for Non-Quasi-Cyclic LDPC Codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.

Blind Recognition of Non-Binary LDPC Codes Based on Ant Colony Optimization

This paper introduces a novel blind recognition of non-binary low-density parity-check(LDPC)codes without a candidate set,using ant colony optimization(ACO)algorithm over additive white Gaussian noise(AWGN)channels.Specifically,the scheme that effectively combines the ACO algorithm and the non-binary elements over finite fields is proposed.Furthermore,an improved,simplified elitist ACO algorithm based on soft decision reliability is introduced to recognize the parity-check matrix over noisy channels.Simulation results show that the recognition rate continuously increases with an increased signalto-noise ratio(SNR)over the AWGN channel.

Quantum quasi-cyclic low-density parity-check error-correcting codes

In this paper, we propose the approach of employing circulant permutation matrices to construct quantum quasicyclic （QC） low-density parity-check （LDPC） codes. Using the proposed approach one may construct some new quantum codes with various lengths and rates of no cycles-length 4 in their Tanner graphs. In addition, these constructed codes have the advantages of simple implementation and low-complexity encoding. Finally, the decoding approach for the proposed quantum QC LDPC is investigated.

Quaternary quasi-cyclic codes

Quasi-cyclic codes of length mn over Z4 are shown to be equivalent to A-submodules of A^n, where A = Z4[x]/（x^m - 1）. In the case of m being odd, all quasi-cyclic codes are shown to be decomposable into the direct sum of a fixed number of cyclic irreducible A-submodules. Finally the distinct quasi-cyclic codes as well as some specific subclasses are enumerated.

Efficient construction and encoding of QC-LDPC codes by cyclic lifting of protographs

Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.

Design of Protograph LDPC-Coded MIMO-VLC Systems with Generalized Spatial Modulation

This paper investigates the bit-interleaved coded generalized spatial modulation(BICGSM) with iterative decoding(BICGSM-ID) for multiple-input multiple-output(MIMO) visible light communications(VLC). In the BICGSM-ID scheme, the information bits conveyed by the signal-domain(SiD) symbols and the spatial-domain(SpD) light emitting diode(LED)-index patterns are coded by a protograph low-density parity-check(P-LDPC) code. Specifically, we propose a signal-domain symbol expanding and re-allocating(SSER) method for constructing a type of novel generalized spatial modulation(GSM) constellations, referred to as SSERGSM constellations, so as to boost the performance of the BICGSM-ID MIMO-VLC systems.Moreover, by applying a modified PEXIT(MPEXIT) algorithm, we further design a family of rate-compatible P-LDPC codes, referred to as enhanced accumulate-repeat-accumulate(EARA) codes,which possess both excellent decoding thresholds and linear-minimum-distance-growth property. Both analysis and simulation results illustrate that the proposed SSERGSM constellations and P-LDPC codes can remarkably improve the convergence and decoding performance of MIMO-VLC systems. Therefore, the proposed P-LDPC-coded SSERGSM-mapped BICGSMID configuration is envisioned as a promising transmission solution to satisfy the high-throughput requirement of MIMO-VLC applications.

Weighted symbol-flipping decoding algorithm for nonbinary LDPC codes with flipping patterns

A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.

Design of good QC-LDPC codes without small girth in the p-plane

A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filtering the bad points, because the designed parity-check matrixes using these points have the short cycles in Tanner graph of codes. Then one of the best points from the residual good points of every line in the p-plane will be found, respectively. The optimal point is also singled out according to the bit error rate （BER） performance of the QC-LDPC codes at last. Explicit necessary and sufficient conditions for the QC-LDPC codes to have no short cycles are presented which are in favor of removing the bad points in the p-plane. Since preventing the short cycles also prevents the small stopping sets, the proposed construction method also leads to QC-LDPC codes with a higher stopping distance.

Construction of protograph LDPC codes with circular generator matrices

The application of protograph low density parity check （LDPC） codes involves the encoding complexity problem. Since the generator matrices are dense, and if the positions of ＂1＂ s are irregularity, the encoder needs to store every ＂1＂ of the generator matrices by using huge chip area. In order to solve this problem, we need to design the protograph LDPC codes with circular generator matrices. A theorem concerning the circulating property of generator matrices of nonsingular protograph LDPC codes is proposed. The circulating property of generator matrix of nonsingular protograph LDPC codes can be obtained from the corresponding quasi-cyclic parity check matrix. This paper gives a scheme of constructing protograph LDPC codes with circulating generator matrices, and it reveals that the fast encoding algorithm of protograph LDPC codes has lower encoding complexity under the condition of the proposed theorem. Simulation results in ad- ditive white Gaussian noise （AWGN） channels show that the bit error rate （BER） performance of the designed codes based on the proposed theorem is much better than that of GB20600 LDPC codes and Tanner LDPC codes.

Doped low-density parity-check codes

In this paper,we propose a doping approach to lower the error floor of Low-Density Parity-Check(LDPC)codes.The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code.Accordingly,an algorithm for selecting the information bits of the short code is proposed,and a specific two-stage decoding algorithm is presented.Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10^(-6)Furthermore,the proposed design can lower the error floor of original LDPC Codes.

Relative-Residual-Based Dynamic Schedule for Belief Propagation Decoding of LDPC Codes

Two Relative-Residual-based Dynamic Schedules(RRDS) for Belief Propagation(BP) decoding of Low-Density Parity-Check(LDPC) codes are proposed,in which the Variable code-RRDS(VN-RRDS) is a greediness-reduced version of the Check code-RRDS(CN-RRDS).The RRDS only processes the variable(or check) node,which has the maximum relative residual among all the variable(or check) nodes in each decoding iteration,thus keeping less greediness and decreased complexity in comparison with the edge-based Variable-to-Check Residual Belief Propagation(VC-RBP) algorithm.Moreover,VN-RRDS propagates first the message which has the largest residual based on all check equations.For different types of LDPC codes,simulation results show that the convergence rate of RRDS is higher than that of VC-RBP while keeping very low computational complexity.Furthermore,VN-RRDS achieves faster convergence as well as better performance than CN-RRDS.

Construction of time-frequency codes based on protograph LDPC codes in OFDM communication systems

This paper proposes a scheme to construct time- frequency codes based on protograph low density parity check （LDPC） codes in orthogonal frequency division multiplexing （OFDM） communication systems. This approach synthesizes two techniques： protograph LDPC codes and OFDM. One symbol of encoded information by protograph LDPC codes corresponds to one sub-carrier, namely the length of encoded information equals to the number of sub-carriers. The design of good protograph LDPC codes with short lengths is given, and the proposed proto- graph LDPC codes can be of fast encoding, which can reduce the encoding complexity and simplify encoder hardware implementa- tion. The proposed approach provides a higher coding gain in the Rayleigh fading channel. The simulation results in the Rayleigh fading channel show that the bit error rate （BER） performance of the proposed time-frequency codes is as good as random LDPC- OFDM codes and is better than Tanner LDPC-OFDM codes under the condition of different fading coefficients.

PERFORMANCE OF SIMPLE-ENCODING IRREGULAR LDPC CODES BASED ON SPARSE GENERATOR MATRIX

A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the encoding complexity while maintaining the same decoding complexity as traditional regular LDPC （H-LDPC） codes defined by the sparse parity check matrix. Simulation results show that the performance of the proposed irregular LDPC codes can offer significant gains over traditional LDPC codes in low SNRs with a few decoding iterations over an additive white Gaussian noise （AWGN） channel.

NEW CONSTRUCTIONS OF LDPC CODES BASED ON CIRCULANT PERMUTATION MATRICES FOR AWGN CHANNEL

Two new design approaches for constructing Low-Density Parity-Check(LDPC) codes are proposed.One is used to design regular Quasi-Cyclic LDPC(QC-LDPC) codes with girth at least 8.The other is used to design irregular LDPC codes.Both of their parity-check matrices are composed of Circulant Permutation Matrices(CPMs).When iteratively decoded with the Sum-Product Algorithm(SPA),these proposed codes exhibit good performances over the AWGN channel.

Construction of LDPC Codes for the Layered Decoding Algorithm

Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,

Lowering the Error Floor of ADMM Penalized Decoder for LDPC Codes

Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.