Multi-segmented nanowires for vortex magnetic domain wall racetrack memory

A vortex domain wall's(VW) magnetic racetrack memory's high performance depends on VW structural stability,high speed, low power consumption and high storage density. In this study, these critical parameters were investigated in magnetic multi-segmented nanowires using micromagnetic simulation. Thus, an offset magnetic nanowire with a junction at the center was proposed for this purpose. This junction was implemented by shifting one portion of the magnetic nanowire horizontally in the x-direction(l) and vertically(d) in the y-direction. The VW structure became stable by manipulating magnetic properties, such as magnetic saturation(M_(4)) and magnetic anisotropy energy(K_(u)). In this case, increasing the values of M_(4) ≥ 800 kA/m keeps the VW structure stable during its dynamics and pinning and depinning in offset nanowires,which contributes to maintenance of the storage memory's lifetime for a longer period. It was also found that the VW moved with a speed of 500 m/s, which is desirable for VW racetrack memory devices. Moreover, it was revealed that the VW velocity could be controlled by adjusting the offset area dimensions(l and d), which helps to drive the VW by using low current densities and reducing the thermal-magnetic spin fluctuations. Further, the depinning current density of the VW(J_(d)) over the offset area increases as d increases and l decreases. In addition, magnetic properties, such as the M_(4) and K_(u),can affect the depinning process of the VW through the offset area. For high storage density, magnetic nanowires(multisegmented) with four junctions were designed. In total, six states were found with high VW stability, which means three bits per cell. Herein, we observed that the depinning current density(J_(d)) for moving the VW from one state to another was highly influenced by the offset area geometry(l and d) and the material's magnetic properties, such as the M_(4) and K_(u).

Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs

The key to high performance for GPU architecture lies in its massive threading capability to drive a large number of cores and enable execution overlapping among threads. However, in reality, the number of threads that can simultaneously execute is often limited by the size of the register file on GPUs. The traditional SRAM-based register file takes up so large amount of chip area that it cannot scale to meet the increasing demand of GPU applications. Racetrack memory （RM） is a promising technology for designing large capacity register file on GPUs due to its high data storage density. However, without careful deployment of RM-based register file, the lengthy shift operations of RM may hurt the performance. In this paper, we explore RM for designing high-performance register file for GPU architecture. High storage density RM helps to improve the thread level parallelism （TLP）, but if the bits of the registers are not aligned to the ports, shift operations are required to move the bits to the access ports before they are accessed, and thus the read/write operations are delayed. We develop an optimization framework for RM-based register file on GPUs, which employs three different optimization techniques at the application, compilation, and architecture level, respectively. More clearly, we optimize the TLP at the application level, design a register mapping algorithm at the compilation level, and design a preshifting mechanism at the architecture level. Collectively, these optimizations help to determine the TLP without causing cache and register file resource contention and reduce the shift operation overhead. Experimental results using a variety of representative workloads demonstrate that our optimization framework achieves up to 29% （21% on average） performance improvement.

Shape-influenced non-reciprocal transport of magnetic skyrmions in nanoscale channel

Skyrmions, with their vortex-like structures and inherent topological protection, play a pivotal role in developing innovative low-power memory and logic devices. The efficient generation and control of skyrmions in geometrically confined systems are crucial for the development of skyrmion-based spintronic devices. In this study, we focus on investigating the non-reciprocal transport behavior of skyrmions and their interactions with boundaries of various shapes. The shape of the notch structure in the nanotrack significantly affects the dynamic behavior of magnetic skyrmions. Through micromagnetic simulation, the non-reciprocal transport properties of skyrmions in nanowires with different notch structures are investigated in this work.

Realization of skyrmion shift register

The big data explosion demands novel data storage technology. Among many different approaches, solitonic racetrack memory devices hold great promise for accommodating nonvolatile and low-power functionalities. As representative topological solitons, magnetic skyrmions are envisioned as potential information carriers for efficient information processing. While their advantages as memory and logic elements have been vastly exploited from theoretical perspectives, the corresponding experimental efforts are rather limited. These challenges, which are key to versatile skyrmionic devices, will be studied in this work. Through patterning concaved surface topography with designed arrays of indentations on standard Si/SiO_(2) substrates, we demonstrate that the resultant non-flat energy landscape could lead to the formation of hexagonal and square skyrmion lattices in Ta/CoFeB/MgO multilayers. Based on these films, one-dimensional racetrack devices are subsequently fabricated, in which a long-distance deterministic shifting of skyrmions between neighboring indentations is achieved at room temperature. Through separating the word line and the bit line, a prototype shift register device, which can sequentially generate and precisely shift complex skyrmionic data strings, is presented. The deterministic writing and longdistance shifting of skyrmionic bits can find potential applications in transformative skyrmionic memory,logic as well as the in-memory computing devices.

Current-driven transformations of a skyrmion tube and a bobber in stepped nanostructures of chiral magnets

Magnetic skyrmion tubes and bobbers are two types of different nanoscale spin configurations that can coexist in nanostructures of chiral magnets.They are then proposed to be utilized as binary bits to build racetrack memory devices.The ability to manipulate the two magnetic objects controllably by current in nanostructures is the prerequisite to realize the device.Here,we demonstrate by numerical simulations that a magnetic bobber and a skyrmion tube can be transformed to each other using spinpolarized current in nanostripes with stepped shape.We also show such stepped nanostructures can be readily applied as the write head for the skyrmion-bobber-based racetrack memory.