Research for radiation-hardened high-voltage SOI LDMOS

Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose(TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner,and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad(Si).

Dynamic modeling of total ionizing dose-induced threshold voltage shifts in MOS devices

The total ionizing dose(TID) effect is a key cause for the degradation/failure of semiconductor device performance under energetic-particle irradiation. We developed a dynamic model of mobile particles and defects by solving the rate equations and Poisson's equation simultaneously, to understand threshold voltage shifts induced by TID in silicon-based metal–oxide–semiconductor(MOS) devices. The calculated charged defect distribution and corresponding electric field under different TIDs are consistent with experiments. TID changes the electric field at the Si/SiO_(2) interface by inducing the accumulation of oxide charged defects nearby, thus shifting the threshold voltage accordingly. With increasing TID, the oxide charged defects increase to saturation, and the electric field increases following the universal 2/3 power law. Through analyzing the influence of TID on the interfacial electric field by different factors, we recommend that the radiation-hardened performance of devices can be improved by choosing a thin oxide layer with high permittivity and under high gate voltages.

Design and implementation of a programming circuit in radiation-hardened FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory（SRAM）-based FPGA fabricated by a 0.5μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1×10~5 rad（Si）,dose rate survivability of 1.5×10^（11） rad（Si）/s and neutron fluence immunity of 1×10^（14） n/cm^2.

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

With the critical charge reduced to generate a single event effect （SEE） and high working frequency for a nanometer integrated circuit, the single event effect （SET） becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n＋ guard ring and p＋ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient （SET） pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET＇s pulse- width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV-cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETefr from 12.5 MeV.cm2/mg to 79.5 MeV-cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer （LETeff value is larger than 40 MeV-cm2/mg. The test results also show that the hardened commercial standard cell＇s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

Performance comparison of radiation-hardened layout techniques

Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space applications.The readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a discriminator.An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^2.The input energy range is from 5 to 350 keV.For this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/channel.Through the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）Am.The radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.

A radiation-hardened SOl-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell （LC）,with a multi-mode based on 3-input look-up-table（LUT）,increases logic density about 12%compared to a traditional 4-input LUT.The logic block（LB）,consisting of 2 LCs,can be used in two functional modes：LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly.Moreover,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad（Si）,a dose rate survivability of 1.5×10^（11）rad（Si）/s and a neutron fluence immunity of 1×10^（14） n/cm^2.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.

Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-level RHBD（radiation-hardening by design） techniques were employed.Adaptive slope compensation was used to improve the inherent instability.The H-gate MOS transistors,annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose.A boost converter was fabricated by a standard commercial 0.35μm CMOS process.The hardened design converter can work properly in a wide range of total dose radiation environments,with increasing total dose radiation.The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.