The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes

As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation（STI）. The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional（3D） technology computer-aided design simulation（TCAD） results show that this technique can achieve efficient SET mitigation.

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

Radiation protection designs of the linac for the HEPS

Purpose The high-energy photon source(HEPS)is the first fourth-generation light source under construction in China.It is designed to operate at an average current of 200 mA stored beam current with a top-up model at 6 GeV energy.Considering the linac radiation shielding design,a suitable beam loss scenario,optimized thickness for the bulk shielding and detailed structure design for dumps should be proposed.In this paper,the beam loss scenarios were determined and categorized as normal;the dose limits were presented;using these scenarios and the dose limits,the thickness of the linac tunnel was calculated and detailed designs of the main beam dumps were established.The material selection and size setting of the low-power electron beam dump were discussed.Method The Monte Carlo code is a good choice to simulate the radiation analysis.And the iSHIELD11 was used to verify the simulation calculations.Result and conclusion The designs of the linac bulk shield and dumps satisfied the requirements of radiation protection.

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Since single event transient pulse quenching can reduce the SET(single event transient) pulsewidths effectively,the charge collected by passive device should be maximized in order to minimize the propagated SET.From the perspective of the layout and circuit design,the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay,which sheds new light on the radiation-hardened ICs(integrated circuits) design.Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET(linear energy transfer) of incident particles,thus the defining of the LET threshold should be noted when SET/SEU(single event upset) occurs for the radiation-hardened design.The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low.Therefore,radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process

A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.