针对Turbo码全并行译码算法译码迭代次数多、硬件消耗大的问题,提出了一种基于RADIX-4的改进译码算法。将译码算法中状态转移图的相邻两步状态合并为一步计算,译码时以"比特对"的形式操作进行迭代。在保留译码最大并行度同时...针对Turbo码全并行译码算法译码迭代次数多、硬件消耗大的问题,提出了一种基于RADIX-4的改进译码算法。将译码算法中状态转移图的相邻两步状态合并为一步计算,译码时以"比特对"的形式操作进行迭代。在保留译码最大并行度同时,译码计算单元使用量减少一半,显著降低了Turbo码全并行译码算法的运算复杂度和存储开销。仿真结果表明,在相同迭代次数条件下,该方法的译码性能较全并行译码算法平均提高约0.5 d B。展开更多
In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
文摘针对Turbo码全并行译码算法译码迭代次数多、硬件消耗大的问题,提出了一种基于RADIX-4的改进译码算法。将译码算法中状态转移图的相邻两步状态合并为一步计算,译码时以"比特对"的形式操作进行迭代。在保留译码最大并行度同时,译码计算单元使用量减少一半,显著降低了Turbo码全并行译码算法的运算复杂度和存储开销。仿真结果表明,在相同迭代次数条件下,该方法的译码性能较全并行译码算法平均提高约0.5 d B。
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
