Dynamic Reconfigurable Structure with Rate Distortion Optimization

The Rate Distortion Optimization(RDO)algorithm in High Efficiency Video Coding(HEVC)has many iterations and a large number of calculations.In order to decrease the calculation time and meet the requirements of fast switching of RDO algorithms of different scales,an RDO dynamic reconfigurable structure is proposed.First,the Quantization Parameter(QP)and bit rate values were loaded through an H⁃tree Configurable Network(HCN),and the execution status of the array was detected in real time.When the switching request of the RDO algorithm was detected,the corresponding configuration information was delivered.This self⁃reconfiguration implementation method improved the flexibility and utilization of hardware.Experimental results show that when the control bit width was only increased by 31.25%,the designed configuration network could increase the number of controllable processing units by 32 times,and the execution cycle was 50%lower than the same type of design.Compared with previous RDO algorithm,the RDO algorithm implemented on the reconfigurable array based on the configuration network had an average operating frequency increase of 12.5%and an area reduction of 56.4%.

An Improved Rate Control Method Based on Modification at Scene Change for H.264

This paper presents an improved rate control method for H.264. First, the scene changes are detected by the average absolute difference of the brightness histograms between the adjacent frames. Then, the bit allocation and quantization parameters are adjusted, using a certain threshold. In addition, the calculation of the mean absolute difference （MAD） is modified in an alternative way, which makes the rate distortion optimization （RDO） more accurate. Extensive simulation results show that the proposed method, compared with G012, can improve the average peak signal-to-noise ratio （PSNR） and moderate the image quality.

Improved algorithm for RDO in JPEG2000 encoder and its IC design

An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware architecture which includes control unit, memory, divider, data converter is also given to implement the algorithm. The circuit based on the improved algorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.

Improved rate-distortion optimized video coding using non-integer bit estimation and multiple Lambda search

Many modern video encoders use the Lagrangian rate-distortion optimization （RDO） algorithm for mode deci- sions during the compression procedure. For each encoding stage, this approach involves minimizing a cost, which is a function of rate, distortion and a multiplier called Lambda. This paper proposes to improve the RDO process by applying two modifications. The first modification is to increase the ac- curacy of rate estimation, which is achieved by computing a non-integer number of bits for arithmetic coding of the syntax elements. This leads to a more accurate cost computation and therefore a better mode decision. The second modification is to search and adjust the value of Lambda based on the char- acteristics of each coding stage. For the encoder used, this paper proposes to search multiple values of Lambda for the intra-4x4 mode decision. Moreover, a simple shift in Lambda value is proposed for motion estimation. Each of these modi- fications offers a certain gain in RDO performance, and, when all are combined, an average bit-rate saving of up to 7.0% can be achieved for the H.264/AVC codec while the same concept is applicable to the H.265/HEVC codec as well. The extra added complexity is contained to a certain level, and is also adjustable according to the processing resources available.

Research on variable block size motion estimation algorithm for airborne image

A fast motion estimation algorithm for variable block-size using the ＂line scan and block merge procedure＂ is proposed for airborne image compression modules.Full hardware implementation via FPGA is discussed in detail.The proposed pipelined architecture based on the line scan algorithm is capable of calculating the required 41 motion vectors of various size blocks supported by H.264 within a 16 × 16 block in parallel.An adaptive rate distortion cost function is used for various size block decision.The motion vectors of adjacent small blocks are merged to predict the motion vectors of larger blocks for reducing computation.Experimental results show that our proposed method has lower computational complexity than full search algorithm with slight quality decrease and little bit rate increase.Due to the high real-time processing speed it can be easily realized in hardware.

An Improved Intra-Prediction Algorithm for H.264

H.264 improves the coding efficiency by adopting rate distortion optimization (RDO); however,it yields high computa-tional complexity. In order to reduce the intra-frame coding time,a fast and effective intra-prediction mode selection algorithm is proposed. The minimum sum of absolute differences between sub-block and its marginal weighted-pixels are used for selecting the candidates of prediction modes to speed up the intra-prediction process with an early termination criterion. Experimental results show that the proposed method can reduce the encoding time by more than 63% comparing with JM (Joint Model) software and is better than the previous algorithms,with negligible loss of coding performance.