We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the cur...We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the current.The model is based on the BSIM3v3 model.Instead of using constant threshold voltage and early voltage,as is assumed in the BSIM3v3 model,we define these voltages as functions of the gate-source voltage.The accuracy of the model is verified by comparison with HSPICE for the 90-,65-,45-,and 32-nm CMOS technologies.The model shows better accuracy than the nth-power and BSIM3v3 models.Then,we use the proposed I-V model to calculate the read static noise margin(SNM) of nano-scale conventional 6T static random-access memory(SRAM) cells with high accuracy.We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed.The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-,65-,45-,and 32-nm technologies.Verification in the presence of process variations and negative bias temperature instability(NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.展开更多
Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable ...Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.展开更多
文摘We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the current.The model is based on the BSIM3v3 model.Instead of using constant threshold voltage and early voltage,as is assumed in the BSIM3v3 model,we define these voltages as functions of the gate-source voltage.The accuracy of the model is verified by comparison with HSPICE for the 90-,65-,45-,and 32-nm CMOS technologies.The model shows better accuracy than the nth-power and BSIM3v3 models.Then,we use the proposed I-V model to calculate the read static noise margin(SNM) of nano-scale conventional 6T static random-access memory(SRAM) cells with high accuracy.We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed.The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-,65-,45-,and 32-nm technologies.Verification in the presence of process variations and negative bias temperature instability(NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.
文摘Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.
