Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.

Readout circuit with nonuniformity correction for the uncooled microbolometer

The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.

Low Noise Readout Circuit for Biosensor SoC

Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.

New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.

A 97 dB dynamic range CSA-based readout circuit with analog temperature compensation for MEMS capacitive sensors

Abstract： This paper presents a charge-sensitive-amplifier （CSA） based readout circuit for capacitive microelectro-mechanical-system （MEMS） sensors. A continuous-time （CT） readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits. An operational trans-conductance amplifier （OTA） structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal. An analog temperature compensation method is proposed, which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity. The chip is designed and implemented in a 0.35μm CMOS process and is 2.1 × 2.1 mm2 in area. The measurement shows that the readout circuit achieves 0.9 aF/√H capacitive resolution, 97 dB dynamic range in 100 Hz signal bandwidth, and 0.8 mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.

Particle detector readout integrated circuit of 0.18μm technology with 164 e equivalent noise charge

Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.

高速数字化三维集成式CCD-CMOS图像传感器

为了解决CCD与CMOS工艺兼容性低、互连集成制作难度大,以及芯片间接口匹配和高性能兼备等问题,对CCD器件拓扑结构与像元、CMOS读出电路、三维异质互连集成及高密度引脚封装等技术进行研究,提出了一种1024×256阵列规模的集成式CCD-CMOS图像传感器。该器件实现了CCD信号的高精度数字化处理、高速输出及多芯粒的技术融合,填补了国内CCDCMOS三维集成技术空白。测试结果表明:集成CCD-CMOS器件的光响应和成像功能正常,双边成像效果良好,图像无黑条和坏列,互连连通率(99.9%)满足三维集成要求,实现了集成式探测器件的大满阱高灵敏度成像(满阱电子数达165.28ke^(-)、峰值量子效率达86.1%)、高精度数字化(12bit)和高速输出(行频率达100.85kHz),满足集成化、数字化、小型化的多光谱探测成像系统要求。

基于磁性传感器的低失调温度补偿接口电路设计

面向磁性传感器在物联网(IoT)技术中的广泛应用,该文基于180 nm CMOS工艺设计了一种具有低失调电压,低温度漂移特性的霍尔传感器接口电路。针对霍尔传感器灵敏度的温度漂移特性,该文设计了一种感温电路并与查表法相结合,调节可编程增益放大器(PGA)的增益有效地降低了霍尔传感器的温度系数(TC)。在此基础上,通过在信号主通路中使用相关双采样(CDS)技术,极大程度上消除了霍尔传感器的失调电压。仿真结果表明,在–40°C~125°C温度范围内,霍尔传感器的TC从966.4 ppm/°C减小到了58.1 ppm/°C。信号主通路的流片结果表明,霍尔传感器的失调电压从25 mV左右减小到了4 mV左右,霍尔传感器的非线性误差为0.50%。芯片的总面积为0.69 mm^(2)。

消除CDS折叠效应的增益自适应红外焦平面读出电路

高动态范围是红外焦平面探测技术的先进发展方向之一。高集成度像元读出电路的动态范围受到小电荷存储容量和噪声的限制。所设计的增益自适应像元读出电路,小信号下为电容反馈跨阻放大器(CTIA),大信号下自动转换为变阻抗电阻反馈跨阻放大器(RTIA),实现小信号大增益、大信号小增益的自动切换,将集成3.86 fF积分电容的CTIA电荷容量拓展到1.63 Me^(–)。在15μm像元中心距的像元内集成相关双采样(CDS)结构,大幅减小噪声。对CDS大信号注入产生的折叠效应进行理论分析,并设计抗折叠结构。采用180 nm 3.3V CMOS工艺,完成640×512规模的读出电路的设计、仿真、流片、测试。测试结果显示,该电路可消除CDS折叠效应,噪声电子数17 e^(–),动态范围拓展到99.66 dB。

高光谱应用的带可调复位时间CDS的低噪声红外焦平面读出电路

低辐射量的高光谱应用对红外焦平面读出电路(ROIC)提出了低噪声的设计要求。相关双采样(CDS)是常用的减少噪声的结构。本文通过调节钳位和采样保持之间的时间间隔来改进CDS,可灵活消除低频噪声。采用180 nm CMOS工艺设计和制造了640×512规模、15μm像元中心距的读出电路。输入级集成了低噪声CTIA与本文提出的可调复位时间CDS(AICDS),所设计的时序产生器使CDS复位时间可以延长0~270个时钟周期。通过延长复位时间减少这个时间间隔,噪声电子数可以由39 e^(-)减少到18.3 e^(-)。SPECTRE仿真结果和实验测试结果证实了提出的AICDS结构可以提升高光谱应用读出电路的噪声性能,因此可以广泛应用。

一种高帧频大动态范围像素级数字化读出电路设计

与短波和中波器件相比,长波红外探测器具有较大的光电流和暗电流,故需要强大的电荷存储能力。而使用传统的模拟像元读出电路技术会严重受限于电荷存储能力,使得长波探测器的动态范围和信噪比难以提升,从而制约着长波红外成像系统的发展和应用。提出一种像素级数字读出电路技术,通过数字积分克服了传统模拟积分方案电荷存储能力受限的缺陷,实现了探测器的数字信号输出,能够极大提高探测器的动态范围、抗干扰能力和帧频。该技术是提升长波探测器性能的有效途径。基于该技术设计了一款像元间距为30 m的320×256数字读出电路,其输出以低压差分信号(Low Voltage Differential Signal,LVDS)方式传输。仿真结果显示,该电路的最高帧频可达1000 Hz,动态范围大于95 dB。

一种具有积分电容复用功能的红外读出电路设计

为提高长波红外探测器的电荷处理能力,提出了一种积分电容复用技术。该技术将读出电路阵列分为奇偶行两个部分,使奇偶行像素分开进行积分读出。当所有的奇行像素积分时,所有的偶行像素均不进行积分。奇行像素复用偶行像素的积分电容,奇行像素积分结束后按行列顺序依次读出。同样地,当所有偶行像素积分时,奇行像素不进行积分,偶行像素复用奇行像素的电容,积分完成后偶行像素按顺序读出。相比于使用叠层电容来提高电荷处理能力的方法,积分电容复用技术更加有效且不受工艺限制。仿真结果表明,积分电容复用技术可将像素的等效积分电容提升至原来的2倍,使读出电路的电荷处理能力从20 Me^(-)提升至40 Me^(-)。

一款多色叠层量子阱红外探测器的读出电路设计

一款完整的红外焦平面探测器主要包含探测器件、读出电路、封装结构和制冷组件。目前根据不同应用场景,探测波段范围不断变宽、探测灵敏度需求提高、成像速度要求加快,对探测器设计提出了更严格、更复杂的指标要求。其中,读出电路将探测光信号转换为电信号传输至系统,是探测器组件的关键核心模块。本文设计了一款对应多色叠层量子阱型器件的红外焦平面探测器读出电路,能够实现同时间、同空间对四波段信号进行探测,并且同时读出,四波段信号的探测积分与读出之间没有互相干扰。探测器规格640×512,像元间距50μm(四波段),各波段信号可实现分时积分、分别可调,采用边积分边读出工作模式,读出帧频可达到四波段探测时≥50 Hz,电路噪声≤0.5 mV,动态范围≥70 dB,电功耗≤600 mW,是一款超大规模低噪声高帧频的高性能读出电路。

多光谱TDI-CMOS图像传感器读出电路设计

针对3D集成式多光谱TDI-CMOS图像传感器的数字化处理和高速读出需求,为了解决与TDICCD探测器的整体布局、物理尺寸和接口的匹配性和一致性问题,研制了适用于五谱段TDICCD的CMOS读出电路芯片。该读出电路芯片创新地设计了一种使用多相位ADC时钟、支持相关多次采样的新型列级单斜ADC电路结构,实现了TDICCD信号的数字化和高速输出,有效提升了探测器的动态范围和噪声指标。流片测试结果表明:读出电路芯片的功能正常,集成式TDICCD的成像效果良好,新型列级ADC工作正常,读出电路以最小9.5μs的行周期输出14 bit数据,相关多次采样具备降低输出信号噪声的作用,实现了TDICCD信号的高精度数字化处理和高速输出,满足3D集成式TDI-CMOS图像传感器的研制要求。

SPAD阵列读出电路关键技术与发展趋势(特邀)

首先针对SPAD阵列读出电路的特点,将电路主要分成接口电路与信号处理电路两大部分,其次根据单光子雪崩光电探测器的阵列的不同应用场景,阐述了集成读出电路中核心电路模块设计的关键技术。分别从SPAD的接口电路设计、两种典型应用成像模式(光子计时、光子计数)中核心电路的设计方面,详细分析此类电路的关键技术以及国内外研究团队在此类电路的研究进展与存在的问题。最后根据目前国内外研究的进展情况,分析了SPAD阵列集成读出电路的发展趋势以及各类电路存在的设计重点与难点,为SPAD阵列读出电路的设计提供一些参考。

一种高增益电压放大电路的设计与实验

反馈放大电路和滤波电路在理论分析和实践教学中都比较重要,然而在传统的电路实验教学中,少有将二者结合的任务驱动型电路设计实验。从太赫兹探测器读出电路这一实际的科研任务出发,设计了一种由前置放大、二级放大和有源滤波三个模块级联组成的高增益低噪声放大电路,并完成了仿真分析、参数调整优化和实验验证。这一内容有助于培养学生基于实际需求的电路综合设计、仿真分析和动手实践的能力。

像素级模数转换器研究进展

像素级模数转换器因其独特的集成位置而具有高帧频、大动态范围、低功耗及低噪声等优点,广泛应用于红外、可见光及太赫兹成像等领域。文章介绍了主流像素级模数转换器结构的原理,综述了像素级模数转换器在动态范围、功耗、面积及噪声等性能参数的研究进展,最后分别比较和总结了各改进方向的几种关键技术并做出展望。

混合像素传感器阵列外围拥塞缓解读出电路设计

介绍了一种混合像素传感器的外围数字读出电路,适用于高能粒子探测、生物医学成像等领域。该外围读出电路由拥塞缓解电路、持续仲裁电路与循环仲裁电路组成。分析了粒子集群的特征和不同数据路由策略对电路的影响,采用间隔n列通道共享存储器与持续/循环仲裁两种策略,缓解瞬时大量粒子击中时的信息损失问题。仿真结果表明,拥塞缓解电路较传统电路在200 kHz对撞频率下,数据读出能力提升43%,当传感器阵列击中比例达3%时,粒子信息损失减少23.43%。采用0.13μm CMOS工艺,64通道拥塞缓解外围数字电路的面积为219664μm^(2),对比未经拥塞缓解处理电路,数字外围电路面积减小13.26%。

基于隧穿磁阻磁强计的软物理不可克隆函数设计

隧穿磁阻(TMR)传感器相比于其他类型磁阻传感器功耗更低、灵敏度更高、可靠性更好,在军事和民用等领域有着广阔的应用前景。该文针对TMR传感器的微弱信号检测和安全防护等问题,提出一种高精度TMR传感器读取专用集成电路(ASIC)和提取传感器物理不可克隆函数(PUF)特性的设计方案。该方案通过设计前端低噪声仪表放大器和高精度模数转换器,并结合斩波技术和纹波抑制技术,实现高精度信号读取和模数转换;利用具备数字输出功能的TMR磁强计比较不同传感器零位偏差,采用多位随机平衡算法完成TMR磁强计的软PUF设计,可产生128 bit PUF响应。TMR传感器读取ASIC利用上海华虹0.35μm CMOS工艺完成流片,并测试磁强计功能和TMR-PUF性能。实验结果表明,在5V电源电压下,TMR磁强计系统功耗约10 mW,噪底可达–140 dBV,3次谐波失真–107 dB;TMR-PUF的唯一性达到47.8%,稳定性为97.85%,与相关文献比较性能优异。