A low-power complementary metal oxide semiconductor(CMOS) operational amplifier (op-amp) for real-time signal processing of micro air vehicle (MAV) is designed in this paper.Traditional folded cascode architectu...A low-power complementary metal oxide semiconductor(CMOS) operational amplifier (op-amp) for real-time signal processing of micro air vehicle (MAV) is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor(PMOS) differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.展开更多
This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under...This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors (pH electrode, H2S electrode, H2 electrode) and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.展开更多
Although computer architectures incorporate fast processing hardware resources, high performance real-time implementation of a complex control algorithm requires an efficient design and software coding of the algorith...Although computer architectures incorporate fast processing hardware resources, high performance real-time implementation of a complex control algorithm requires an efficient design and software coding of the algorithm so as to exploit special features of the hardware and avoid associated architecture shortcomings. This paper presents an investigation into the analysis and design mechanisms that will lead to reduction in the execution time in implementing real-time control algorithms. The proposed mechanisms are exemplified by means of one algorithm, which demonstrates their applicability to real-time applications. An active vibration control (AVC) algorithm for a flexible beam system simulated using the finite difference (FD) method is considered to demonstrate the effectiveness of the proposed methods. A comparative performance evaluation of the proposed design mechanisms is presented and discussed through a set of experiments.展开更多
In the past decades,physical modeling has been widely used in hydrogeology for teaching,studying and exhibition purposes.Most of these models are used to illustrate hydrogeological profiles,but few can depict three-di...In the past decades,physical modeling has been widely used in hydrogeology for teaching,studying and exhibition purposes.Most of these models are used to illustrate hydrogeological profiles,but few can depict three-dimensional groundwater flows,making it impossible to validate groundwater flows simulated by numerical methods with physical modeling.展开更多
Affected by the Super Typhoon“Mangkhut,”a total of five base towers of a transmission line in the mountainous area of China collapsed.In this paper,a mathematical model is established based on the Shuttle Radar Topo...Affected by the Super Typhoon“Mangkhut,”a total of five base towers of a transmission line in the mountainous area of China collapsed.In this paper,a mathematical model is established based on the Shuttle Radar Topography Mission(SRTM)data near the accident tower.The measured wind speed in the plain area under the mountain is used as the calculation boundary condition.The wind speed at the top of the mountain is calculated by using a numerical simulation method.The design wind speed and calculated wind speed at the tower site are compared,and the influence of wind speed on tower position in this wind disaster accident is analyzed.展开更多
In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware m...In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.展开更多
The implementation method of the IEEE 802.11 Medium Access Control (MAC) protocol is mainly based on DSP (Digital Signal Processor)/ ARM (Advanced Reduced instruction set computer Machine) processor or DSP/ARM IP (Int...The implementation method of the IEEE 802.11 Medium Access Control (MAC) protocol is mainly based on DSP (Digital Signal Processor)/ ARM (Advanced Reduced instruction set computer Machine) processor or DSP/ARM IP (Intellectual Property) core. This paper presents a method based on Nios II soft-core processor embedded in Altera’s Cyclone FPGA (Field Programmable Gate Array) and MicroC/OS-II RTOS (Real-Time Operation System). The benefits and drawbacks of above methods are compared, and then the method presented in this paper is described. The hardware and software partitioning are discussed; the hardware architecture is also illustrated and the MAC software programming is described in detail. The presented method has some advantages, such as low cost, easy-implementation and very suitable for the implementation of IEEE 802.11 MAC in research stage.展开更多
To satisfy the needs of modem pre-cision agriculture, a Precision Agriculture Sensing System (PASS) is designed, which is based on wireless multimedia sensor network. Both hardware and software of PASS are tai-lored...To satisfy the needs of modem pre-cision agriculture, a Precision Agriculture Sensing System (PASS) is designed, which is based on wireless multimedia sensor network. Both hardware and software of PASS are tai-lored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bit-map index reliable data transmission mecha-nism is proposed. And a battery-array switch-ing system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.展开更多
The choice of methods or design languages is a crucial phase in the development of systems and software, also for real time and embedded systems. An open question that remains in the design of these types of systems i...The choice of methods or design languages is a crucial phase in the development of systems and software, also for real time and embedded systems. An open question that remains in the design of these types of systems is to build a method, or to choose one among those existing, capable to cover the life cycle of a project, and particularly the development phases. This article contributes to answer the question, by proposing an approach based on a multi-criteria comparative study, of few languages and methods dedicated to the design of real time and embedded systems. The underlying objective of this work is to present to designers a wide range of approaches, and elements that can guide their choices. In order to reach this goal, we propose different comparison criteria. Each criterion is divided into sub-criteria, so that the designers can refine their choices according to the qualities they prefer and wish to have in the method or language. We also define a rating scale which is used to assess the retained languages and methods. The scores obtained from this assessment are presented in tables, one table per criterion, followed by a summary table giving the overall scores. Graphics built from these tables are provided and intend to facilitate the judgement and thus the choice of the designers.展开更多
During the whole service lifetime of aircraft structures with composite materials,impacts are inevitable and can usually cause severe but barely visible damages.Since the occurrences of impact are random and unpredict...During the whole service lifetime of aircraft structures with composite materials,impacts are inevitable and can usually cause severe but barely visible damages.Since the occurrences of impact are random and unpredictable,it is a hotspot direction to develop an online impact monitoring system that can meet strict limitations of aerospace applications including small size,light weight,and low power consumption.Piezoelectric(PZT)sensor,being able to generate impact response signals with no external power and cover a large-scale structure with only a small amount of them,is a promising choice.Meanwhile,for real systems,networks with multiple nodes are normally required to monitor large-scale structures in a global way to identify any impact localization confliction,yet the existing studies are mostly evaluated with single nodes instead of networks.Therefore,in this paper,based on a new low-power node designed,a Bluetooth-based digital impact monitoring PZT sensor network is proposed for the first time with its global confliction-solving impact localization method.Evaluations of the system as a network are researched and analyzed on a complex real aircraft wing box for a global confliction-solving impact localization,showing a satisfying high accuracy.展开更多
Real-time quantitative polymerase chain reaction(qPCR)has gained popularity as a technique to detect and quantify a specific group of target microorganisms from various environmental samples including soil,water,sedim...Real-time quantitative polymerase chain reaction(qPCR)has gained popularity as a technique to detect and quantify a specific group of target microorganisms from various environmental samples including soil,water,sediments,and sludge.Although qPCR is a very useful technique for nucleic acid quantification,accurately quantifying the target microbial group strongly depends on the quality of the primer and probe used.Many aspects of conducting qPCR assays have become increasingly routine and automated;however,one of the most important aspects,designing and selecting primer and probe sets,is often a somewhat arcane process.In many cases,failed or non-specific amplification can be attributed to improperly designed primer-probe sets.This paper is intended to provide guidelines and general principles for designing group-specific primers and probes for qPCR assays.We demonstrate the effectiveness of these guidelines by reviewing the use of qPCR to study anaerobic processes and biologic nutrient removal processes.qPCR assays using group-specific primers and probes designed with this method,have been used to successfully quantify 16S ribosomal Ribonucleic Acid(16S rRNA)gene copy numbers from target methanogenic and ammoniaoxidizing bacteria in various laboratory-and full-scale biologic processes.Researchers with a good command of primer and probe design can use qPCR as a valuable tool to study biodiversity and to develop more efficient control strategies for biologic processes.展开更多
Real-time simulation of large-scale wind farms with detailed modeling can provide accurate insights into system transient behaviors,but entails challenges in computing resources.This paper develops a compact real-time...Real-time simulation of large-scale wind farms with detailed modeling can provide accurate insights into system transient behaviors,but entails challenges in computing resources.This paper develops a compact real-time simulator based on the field programmable gate array(FPGA)for large-scale wind farms,in which the spatial-temporal parallel design method is proposed to address the huge computation resource demand associated with detailed modeling.The wind farm is decoupled into several subsystems based on model consistency,and the electrical system and control system of each subsystem are solved in parallel.Both the module-level pipeline technique and superscalar pipeline technique are introduced to the wind farms’simulation to effectively improve the utilization of hardware resources.In case studies,real-time simulations of two modified wind farms are separately carried out on a single FPGA,including one with 13 permanent magnet synchronous generators under a time-step of 11µs,and the other with 30 squirrel-cage induction generators under a time-step of 8µs.Simulation tests,under different scenarios,are implemented to validate the numerical performance of the real-time simulator,and a comparison with the commercial tool PSCAD/EMTDC demonstrates the accuracy and effectiveness of the proposed design.展开更多
Energy consumption has become a key metric for evaluating how good an embedded system is,alongside more performance metrics like respecting operation deadlines and speed of execution.Schedulability improvement is no l...Energy consumption has become a key metric for evaluating how good an embedded system is,alongside more performance metrics like respecting operation deadlines and speed of execution.Schedulability improvement is no longer the only metric by which optimality is judged.In fact,energy efficiency is becoming a preferred choice with a fundamental objective to optimize the system's lifetime.In this work,we propose an optimal energy efficient scheduling algorithm for aperiodic real-time jobs to reduce CPU energy consumption.Specifically,we apply the concept of real-time process scheduling to a dynamic voltage and frequency scaling(DVFS)technique.We address a variant of earliest deadline first(EDF)scheduling algorithm called energy saving-dynamic voltage and frequency scaling(ES-DVFS)algorithm that is suited to unpredictable future energy production and irregular job arrivals.We prove that ES-DVFS cannot attain a total value greater than C/ˆSα,whereˆS is the minimum speed of any job and C is the available energy capacity.We also investigate the implications of having in advance,information about the largest job size and the minimum speed used for the competitive factor of ES-DVFS.We show that such advance knowledge makes possible the design of semi-on-line algorithm,ES-DVFS∗∗,that achieved a constant competitive factor of 0.5 which is proved as an optimal competitive factor.The experimental study demonstrates that substantial energy savings and highest percentage of feasible job sets can be obtained through our solution that combines EDF and DVFS optimally under the given aperiodic jobs and energy models.展开更多
In real-time applications, compiler-directed dynamic voltage scaling (DVS) could reduce energy consumption efficiently, where compiler put voltage scaling points in the proper places, and the supply voltage and cloc...In real-time applications, compiler-directed dynamic voltage scaling (DVS) could reduce energy consumption efficiently, where compiler put voltage scaling points in the proper places, and the supply voltage and clock frequency were adjusted to the relationship between the reduced time and the reduced workload. This paper presents the optimal configuration of dynamic voltage scaling points without voltage scaling overhead, which minimizes energy consumption. The conclusion is proved theoretically. Finally, it is confirmed by simulations with equally-spaced voltage scaling configuration.展开更多
The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally ...The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.展开更多
Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their ...Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a “transparent” instruction cache, which does not change the existing NV microcontroller’s cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.展开更多
对关节臂式坐标测量机数据采集系统的几个关键点进行了分析设计,其中包括数据同步锁存、对径读数、坐标实时显示.通过可编程逻辑器件(CPLD)与单片机的结合,完成了光栅信号的滤波、4细分、辨向及可逆计数等功能.实验证明,该设计能够准确...对关节臂式坐标测量机数据采集系统的几个关键点进行了分析设计,其中包括数据同步锁存、对径读数、坐标实时显示.通过可编程逻辑器件(CPLD)与单片机的结合,完成了光栅信号的滤波、4细分、辨向及可逆计数等功能.实验证明,该设计能够准确完成测量机的数据采集.
Abstract:
Several key pints of articulated arm - cmm data acquisition system are analyzed and designed, including data synchronous latches, pair-radius readings, and coordinates real-time display. The combination of CPLD and AVR microcontroller completes the functions of grating signal faltering, 4 subdivided, discerning direction and reversible counting, and so on. According to the experiment , the data collection of the machine can be complete accurately.展开更多
基金Sponsored by the National Natural Science Foundation of China (60843005)the Basic Research Foundation of Beijing Institute of Technology(20070142018)
文摘A low-power complementary metal oxide semiconductor(CMOS) operational amplifier (op-amp) for real-time signal processing of micro air vehicle (MAV) is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor(PMOS) differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.
基金supported by the International Cooperative Key Project(Grant No.2004DFA04900)Ministry of Sciences and Technology of PRC,and the National Natural Science Foundation of China (Grant Nos.40637037 and 50675198)
文摘This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors (pH electrode, H2S electrode, H2 electrode) and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.
文摘Although computer architectures incorporate fast processing hardware resources, high performance real-time implementation of a complex control algorithm requires an efficient design and software coding of the algorithm so as to exploit special features of the hardware and avoid associated architecture shortcomings. This paper presents an investigation into the analysis and design mechanisms that will lead to reduction in the execution time in implementing real-time control algorithms. The proposed mechanisms are exemplified by means of one algorithm, which demonstrates their applicability to real-time applications. An active vibration control (AVC) algorithm for a flexible beam system simulated using the finite difference (FD) method is considered to demonstrate the effectiveness of the proposed methods. A comparative performance evaluation of the proposed design mechanisms is presented and discussed through a set of experiments.
基金supported by the State Key Program of National Natural Science of China(Grant No.41130637)
文摘In the past decades,physical modeling has been widely used in hydrogeology for teaching,studying and exhibition purposes.Most of these models are used to illustrate hydrogeological profiles,but few can depict three-dimensional groundwater flows,making it impossible to validate groundwater flows simulated by numerical methods with physical modeling.
基金CRSRI Open Research Program(Project No.CKWV2014202/KY).
文摘Affected by the Super Typhoon“Mangkhut,”a total of five base towers of a transmission line in the mountainous area of China collapsed.In this paper,a mathematical model is established based on the Shuttle Radar Topography Mission(SRTM)data near the accident tower.The measured wind speed in the plain area under the mountain is used as the calculation boundary condition.The wind speed at the top of the mountain is calculated by using a numerical simulation method.The design wind speed and calculated wind speed at the tower site are compared,and the influence of wind speed on tower position in this wind disaster accident is analyzed.
基金supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150+2 种基金the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005
文摘In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.
文摘The implementation method of the IEEE 802.11 Medium Access Control (MAC) protocol is mainly based on DSP (Digital Signal Processor)/ ARM (Advanced Reduced instruction set computer Machine) processor or DSP/ARM IP (Intellectual Property) core. This paper presents a method based on Nios II soft-core processor embedded in Altera’s Cyclone FPGA (Field Programmable Gate Array) and MicroC/OS-II RTOS (Real-Time Operation System). The benefits and drawbacks of above methods are compared, and then the method presented in this paper is described. The hardware and software partitioning are discussed; the hardware architecture is also illustrated and the MAC software programming is described in detail. The presented method has some advantages, such as low cost, easy-implementation and very suitable for the implementation of IEEE 802.11 MAC in research stage.
基金supported in part by the Special Scientific Research Funds for Commonweal Section under Grant No. 200903010the Science and Technology Project of Jiangxi Province under Grants No. 20112BBF60050, No. 20121BBF60058
文摘To satisfy the needs of modem pre-cision agriculture, a Precision Agriculture Sensing System (PASS) is designed, which is based on wireless multimedia sensor network. Both hardware and software of PASS are tai-lored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bit-map index reliable data transmission mecha-nism is proposed. And a battery-array switch-ing system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.
文摘The choice of methods or design languages is a crucial phase in the development of systems and software, also for real time and embedded systems. An open question that remains in the design of these types of systems is to build a method, or to choose one among those existing, capable to cover the life cycle of a project, and particularly the development phases. This article contributes to answer the question, by proposing an approach based on a multi-criteria comparative study, of few languages and methods dedicated to the design of real time and embedded systems. The underlying objective of this work is to present to designers a wide range of approaches, and elements that can guide their choices. In order to reach this goal, we propose different comparison criteria. Each criterion is divided into sub-criteria, so that the designers can refine their choices according to the qualities they prefer and wish to have in the method or language. We also define a rating scale which is used to assess the retained languages and methods. The scores obtained from this assessment are presented in tables, one table per criterion, followed by a summary table giving the overall scores. Graphics built from these tables are provided and intend to facilitate the judgement and thus the choice of the designers.
基金supported by the National Natural Science Foundation of China(Nos.51921003,51975292 and 52275153)the Outstanding Youth Foundation of Jiangsu Province of China(No.BK20211519)+2 种基金the Research Fund of State Key Laboratory of Mechanics and Control of Mechanical Structures,China(Nanjing University of Aeronautics and Astronautics,No.MCMS-I-0521K01)the Fund of Prospective Layout of Scientific Research for Nanjing University of Aeronautics and Astronautics,Chinathe Priority Academic Program Development of Jiangsu Higher Education Institutions,China。
文摘During the whole service lifetime of aircraft structures with composite materials,impacts are inevitable and can usually cause severe but barely visible damages.Since the occurrences of impact are random and unpredictable,it is a hotspot direction to develop an online impact monitoring system that can meet strict limitations of aerospace applications including small size,light weight,and low power consumption.Piezoelectric(PZT)sensor,being able to generate impact response signals with no external power and cover a large-scale structure with only a small amount of them,is a promising choice.Meanwhile,for real systems,networks with multiple nodes are normally required to monitor large-scale structures in a global way to identify any impact localization confliction,yet the existing studies are mostly evaluated with single nodes instead of networks.Therefore,in this paper,based on a new low-power node designed,a Bluetooth-based digital impact monitoring PZT sensor network is proposed for the first time with its global confliction-solving impact localization method.Evaluations of the system as a network are researched and analyzed on a complex real aircraft wing box for a global confliction-solving impact localization,showing a satisfying high accuracy.
基金This work was also supported by the Korea Research Foundation Grant funded by the Korean Government(MOEHRD)by New&Renewable Energy of the Korea Institute of Energy Technology Evaluation and Planning(KETEP)grant(No.20101T100100366).
文摘Real-time quantitative polymerase chain reaction(qPCR)has gained popularity as a technique to detect and quantify a specific group of target microorganisms from various environmental samples including soil,water,sediments,and sludge.Although qPCR is a very useful technique for nucleic acid quantification,accurately quantifying the target microbial group strongly depends on the quality of the primer and probe used.Many aspects of conducting qPCR assays have become increasingly routine and automated;however,one of the most important aspects,designing and selecting primer and probe sets,is often a somewhat arcane process.In many cases,failed or non-specific amplification can be attributed to improperly designed primer-probe sets.This paper is intended to provide guidelines and general principles for designing group-specific primers and probes for qPCR assays.We demonstrate the effectiveness of these guidelines by reviewing the use of qPCR to study anaerobic processes and biologic nutrient removal processes.qPCR assays using group-specific primers and probes designed with this method,have been used to successfully quantify 16S ribosomal Ribonucleic Acid(16S rRNA)gene copy numbers from target methanogenic and ammoniaoxidizing bacteria in various laboratory-and full-scale biologic processes.Researchers with a good command of primer and probe design can use qPCR as a valuable tool to study biodiversity and to develop more efficient control strategies for biologic processes.
基金This work was supported by the National Natural Science Foundation of China under Grant No.U1866207,No.51807131No.51961135101the Swedish Research Council under Grant No.2018-06007。
文摘Real-time simulation of large-scale wind farms with detailed modeling can provide accurate insights into system transient behaviors,but entails challenges in computing resources.This paper develops a compact real-time simulator based on the field programmable gate array(FPGA)for large-scale wind farms,in which the spatial-temporal parallel design method is proposed to address the huge computation resource demand associated with detailed modeling.The wind farm is decoupled into several subsystems based on model consistency,and the electrical system and control system of each subsystem are solved in parallel.Both the module-level pipeline technique and superscalar pipeline technique are introduced to the wind farms’simulation to effectively improve the utilization of hardware resources.In case studies,real-time simulations of two modified wind farms are separately carried out on a single FPGA,including one with 13 permanent magnet synchronous generators under a time-step of 11µs,and the other with 30 squirrel-cage induction generators under a time-step of 8µs.Simulation tests,under different scenarios,are implemented to validate the numerical performance of the real-time simulator,and a comparison with the commercial tool PSCAD/EMTDC demonstrates the accuracy and effectiveness of the proposed design.
文摘Energy consumption has become a key metric for evaluating how good an embedded system is,alongside more performance metrics like respecting operation deadlines and speed of execution.Schedulability improvement is no longer the only metric by which optimality is judged.In fact,energy efficiency is becoming a preferred choice with a fundamental objective to optimize the system's lifetime.In this work,we propose an optimal energy efficient scheduling algorithm for aperiodic real-time jobs to reduce CPU energy consumption.Specifically,we apply the concept of real-time process scheduling to a dynamic voltage and frequency scaling(DVFS)technique.We address a variant of earliest deadline first(EDF)scheduling algorithm called energy saving-dynamic voltage and frequency scaling(ES-DVFS)algorithm that is suited to unpredictable future energy production and irregular job arrivals.We prove that ES-DVFS cannot attain a total value greater than C/ˆSα,whereˆS is the minimum speed of any job and C is the available energy capacity.We also investigate the implications of having in advance,information about the largest job size and the minimum speed used for the competitive factor of ES-DVFS.We show that such advance knowledge makes possible the design of semi-on-line algorithm,ES-DVFS∗∗,that achieved a constant competitive factor of 0.5 which is proved as an optimal competitive factor.The experimental study demonstrates that substantial energy savings and highest percentage of feasible job sets can be obtained through our solution that combines EDF and DVFS optimally under the given aperiodic jobs and energy models.
文摘In real-time applications, compiler-directed dynamic voltage scaling (DVS) could reduce energy consumption efficiently, where compiler put voltage scaling points in the proper places, and the supply voltage and clock frequency were adjusted to the relationship between the reduced time and the reduced workload. This paper presents the optimal configuration of dynamic voltage scaling points without voltage scaling overhead, which minimizes energy consumption. The conclusion is proved theoretically. Finally, it is confirmed by simulations with equally-spaced voltage scaling configuration.
文摘The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.
文摘Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a “transparent” instruction cache, which does not change the existing NV microcontroller’s cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.
文摘对关节臂式坐标测量机数据采集系统的几个关键点进行了分析设计,其中包括数据同步锁存、对径读数、坐标实时显示.通过可编程逻辑器件(CPLD)与单片机的结合,完成了光栅信号的滤波、4细分、辨向及可逆计数等功能.实验证明,该设计能够准确完成测量机的数据采集.
Abstract:
Several key pints of articulated arm - cmm data acquisition system are analyzed and designed, including data synchronous latches, pair-radius readings, and coordinates real-time display. The combination of CPLD and AVR microcontroller completes the functions of grating signal faltering, 4 subdivided, discerning direction and reversible counting, and so on. According to the experiment , the data collection of the machine can be complete accurately.