As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academ...As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academia and industry.However,dynamic reconfigurable computing is not yet mature because of several unsolved problems.This work introduces the concept,architecture,and compilation techniques of dynamic reconfigurable computing.It also discusses the existing major challenges and points out its potential applications.展开更多
Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years.Nodes must advance their energy use for expanding network ...Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years.Nodes must advance their energy use for expanding network lifetime.The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results.Due to different network resource constraints and malicious attacks,security assurance in wireless sensor networks has been a difficult task.The implementation of these features requires larger space due to distributed module.This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission.The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment.The proposed system supports the real-time application in the range of 33 nanoseconds.The obtained results have been compared with the existing Microcontroller-based system.The power consumption of the proposed system consumes only 3.9 mW,and it is only 24%percentage of AT mega-based node architecture.展开更多
Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a ...Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.展开更多
This paper describes a new specialized Reconfigurable Cryptographic for Block ciphersArchitecture(RCBA).Application-specific computation pipelines can be configured according to thecharacteristics of the block cipher ...This paper describes a new specialized Reconfigurable Cryptographic for Block ciphersArchitecture(RCBA).Application-specific computation pipelines can be configured according to thecharacteristics of the block cipher processing in RCBA,which delivers high performance for crypto-graphic applications.RCBA adopts a coarse-grained reconfigurable architecture that mixes the ap-propriate amount of static configurations with dynamic configurations.RCBA has been implementedbased on Altera’s FPGA,and representative algorithms of block cipher such as DES,Rijndael and RC6have been mapped on RCBA architecture successfully.System performance has been analyzed,andfrom the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and ef-ficiency when compared with other implementations.展开更多
基金supported in part by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2018ZX01028201)in part by the National Natural Science Foundation of China (Grant No. 61672317, No. 61834002)in part by the National Key R&D Program of China (Grant No. 2018YFB2202101)
文摘As a computing paradigm that combines temporal and spatial computations,dynamic reconfigurable computing provides superiorities of flexibility,energy efficiency and area efficiency,attracting interest from both academia and industry.However,dynamic reconfigurable computing is not yet mature because of several unsolved problems.This work introduces the concept,architecture,and compilation techniques of dynamic reconfigurable computing.It also discusses the existing major challenges and points out its potential applications.
文摘Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years.Nodes must advance their energy use for expanding network lifetime.The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results.Due to different network resource constraints and malicious attacks,security assurance in wireless sensor networks has been a difficult task.The implementation of these features requires larger space due to distributed module.This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission.The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment.The proposed system supports the real-time application in the range of 33 nanoseconds.The obtained results have been compared with the existing Microcontroller-based system.The power consumption of the proposed system consumes only 3.9 mW,and it is only 24%percentage of AT mega-based node architecture.
基金Project supported by the National Natural Science Foundation of China(Grant No.61073049)the Shanghai Leading Academic Discipline Project(Grant No.J50103)the Doctorate Foundation of Education Ministry of China(Grant No.20093108110016)
文摘Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.
文摘This paper describes a new specialized Reconfigurable Cryptographic for Block ciphersArchitecture(RCBA).Application-specific computation pipelines can be configured according to thecharacteristics of the block cipher processing in RCBA,which delivers high performance for crypto-graphic applications.RCBA adopts a coarse-grained reconfigurable architecture that mixes the ap-propriate amount of static configurations with dynamic configurations.RCBA has been implementedbased on Altera’s FPGA,and representative algorithms of block cipher such as DES,Rijndael and RC6have been mapped on RCBA architecture successfully.System performance has been analyzed,andfrom the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and ef-ficiency when compared with other implementations.
