Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.

Smart Service System(SSS)：A Novel Architecture Enabling Coordination of Heterogeneous Networking Technologies and Devices for Internet of Things

In Internet of Things(IoT), the devices or terminals are connected with each other, which can be very diverse over the wireless networks. Unfortunately, the current devices are not designed to communicate with the collocated devices which employ different communication technologies. Consequently, the communication between these devices will be realized only by using the gateway nodes. This will cause the inefficient use of wireless resources. Therefore, in this paper, a smart service system(SSS) architecture is proposed, which consists of smart service terminal(SST), and smart service network(SSN), to realize the Io T in a general environment with diverse communication networks, devices, and services. The proposed architecture has the following advantages: i) the devices in this architecture cover multiple types of terminals and sensor-actuator devices; ii) the communications network therein is a converged network, and will coordinate multiple kinds of existing and emerging networks. This converged network offers ubiquitous access for various sensors and terminals; iii) the architecture has services and applications covering all smart service areas. It also provides theadaptability to new services and applications. A SSS architecture-based smart campus system was developed and deployed. Evaluation experiments of the proposed smart campus system demonstrate the SSS's advantages over the existing counterparts, and verify the effectiveness of the proposed architecture.

Distributed MPC for Reconfigurable Architecture Systems via Alternating Direction Method of Multipliers

This paper investigates the distributed model predictive control(MPC)problem of linear systems where the network topology is changeable by the way of inserting new subsystems,disconnecting existing subsystems,or merely modifying the couplings between different subsystems.To equip live systems with a quick response ability when modifying network topology,while keeping a satisfactory dynamic performance,a novel reconfiguration control scheme based on the alternating direction method of multipliers(ADMM)is presented.In this scheme,the local controllers directly influenced by the structure realignment are redesigned in the reconfiguration control.Meanwhile,by employing the powerful ADMM algorithm,the iterative formulas for solving the reconfigured optimization problem are obtained,which significantly accelerate the computation speed and ensure a timely output of the reconfigured optimal control response.Ultimately,the presented reconfiguration scheme is applied to the level control of a benchmark four-tank plant to illustrate its effectiveness and main characteristics.

High Efficient Reconfigurable and Self Testable Architecture for Sensor Node

Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years.Nodes must advance their energy use for expanding network lifetime.The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results.Due to different network resource constraints and malicious attacks,security assurance in wireless sensor networks has been a difficult task.The implementation of these features requires larger space due to distributed module.This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission.The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment.The proposed system supports the real-time application in the range of 33 nanoseconds.The obtained results have been compared with the existing Microcontroller-based system.The power consumption of the proposed system consumes only 3.9 mW,and it is only 24%percentage of AT mega-based node architecture.

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

There are numerous goals in next-generation cellular networks(5G),which is expected to be available soon.They want to increase data rates,reduce end-to-end latencies,and improve end-user service quality.Modern networks need to change because there has been a significant rise in the number of base stations required to meet these needs and put the operators’low-cost constraints to the test.Because it can withstand interference from other wireless networks,and Adaptive Complex Multicarrier Modulation(ACMM)system is being looked at as a possible choice for the 5th Generation(5G)of wireless networks.Many arithmetic units need to be used on the hardware side of multicarrier systems to do the pulse-shaping filters and inverse FFT.The main goal of this study is to adapt complex multicarrier modulation(ACMM)for baseband transmission with low complexity and the ability to change it.We found that this is the first recon-figurable architecture that lets you choose how many subcarriers a subband has while still having the same amount of hardware resources as before.Also,under the new design with a single selection line,it selects from a set of filters.The baseband modulating signal is evaluated and tested using a Field-Programmable Gate Array(FPGA)device.This device is available from a commercial source.New technology outperforms current technology in terms of computational com-plexity,simple design,and ease of implementation.Additionally,it has a higher power spectrum density,spectral efficiency,a lower bit error rate,and a higher peak to average power ratio than existing technology.

THE RESEARCH AND DESIGN OF RECONFIGURABLE COMPUTING FOR BLOCK CIPHER

This paper describes a new specialized Reconfigurable Cryptographic for Block ciphersArchitecture(RCBA).Application-specific computation pipelines can be configured according to thecharacteristics of the block cipher processing in RCBA,which delivers high performance for crypto-graphic applications.RCBA adopts a coarse-grained reconfigurable architecture that mixes the ap-propriate amount of static configurations with dynamic configurations.RCBA has been implementedbased on Altera’s FPGA,and representative algorithms of block cipher such as DES,Rijndael and RC6have been mapped on RCBA architecture successfully.System performance has been analyzed,andfrom the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and ef-ficiency when compared with other implementations.

Test access to deeply embedded analog terminals within an A/MS SoC

This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.

Universal Band Pass Sampling Algorithm for Integration of Multiple Wireless Technologies Using Software Defined Radio Platform

Software Defined Radio (SDR) architecture allows us to integrate different mobile technologies using common hardware but with different software modules. To achieve this, we need to keep the signal in digital form for as much portion of the circuitry as possible, so that the implementation could be carried out by programmable digital processors. For this purpose, the incoming radio frequency (RF) signal is down converted to baseband spectrum using band pass sampling method. Research works carried out so far in this field have developed a few algorithms for band pass sampling. But, these algorithms are not much useful for most of the mobile communication systems and they use complex methodology for computing the sampling frequency values. In order to use the SDR platform to integrate all current wireless technologies, an efficient, cost effective and less complex algorithm that can be labelled as universal band pass sampling algorithm is developed in this paper for multiple mobile systems. This algorithm is based on a novel idea of inserting guard bands between the signals which reduces the design complexities of perfect ADC and sharp cut off filters. Using this algorithm, valid sampling frequency ranges and corresponding IF values are calculated for down converting RF signals. The algorithm is tested for six RF signals of different wireless technologies which are integrated and simultaneously down converted using SDR based front end receiver and thus the system multiplies the base station capacity by a factor of six. The simulation results are obtained and shown in this paper which proves that the algorithm developed works well for most of the wireless technologies.

High performance architecture for unified forward and inverse transform of HEVC

High efficiency video coding （HEVC） transform algorithm for residual coding uses 2-dimensional （2D） 4 × 4 transforms with higher precision than H.264＇s 4 ×4 transforms, resulting in increased hardware complexity. In this paper, we present a shared architecture that can compute the 4 ~4 forward discrete cosine transform （DCT） and inverse discrete cosine transform （IDCT） of HEVC using a new mapping scheme in the video processor array structure. The architecture is implemented with only adders and shills to an area-efficient design. The proposed architecture is synthesized using ISE 14.7 and implemented using the BEE4 platform with the Virtex-6 FF1759 LX550T field programmable gate array （FPGA）. The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz. The architecture and its implementation are presented in this paper to demonstrate its programmable and high performance.

A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine （FSM） controllers. Each cluster contains various kinds of ceils that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.

Micro-Task Processing in Heterogeneous Reconfigurable Systems

New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU. © 2017, Shanghai Jiaotong University and Springer-Verlag GmbH Germany.