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Separability Criteria for Quantum Mixed States in Terms of Trace Norm 被引量:5
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作者 赵慧 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第7期1674-1675,共2页
A new necessary conditions for separability of mixed states in bipartite and multipartite quantum systems of arbitrary dimensions are presented. This method requires only a few local measurements. If a quantum state i... A new necessary conditions for separability of mixed states in bipartite and multipartite quantum systems of arbitrary dimensions are presented. This method requires only a few local measurements. If a quantum state in a bipartite (or multipartite) system of arbitrary dimension is separable, we show that the trace norm of a constructive matrix is less than or equal to 1. 展开更多
关键词 reduction criterion DENSITY-MATRICES ENTANGLEMENT
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Design of a(480,240)CMOS Analog Low-Density Parity-Check Decoder
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作者 Hao Zheng Zhe Zhao +1 位作者 Xiangming Li Hangcheng Han 《China Communications》 SCIE CSCD 2017年第8期41-53,共13页
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons... Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works. 展开更多
关键词 LDPC analog decoder handcraft design reduction probability stopping criterion for analog decoding reusable building block
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