The effects of linear falling ramp reset pulse related to addressing operation in an alternating current plasma display panel （AC PDP） were studied. The wall charge waveforms were measured by the electrode balance m...The effects of linear falling ramp reset pulse related to addressing operation in an alternating current plasma display panel （AC PDP） were studied. The wall charge waveforms were measured by the electrode balance method in a 12-inch coplanar AC PDP. The wall charge waveforms show the relationship between the slope ratio of the falling ramp reset pulse and the wall charges at the end of the falling ramp reset pulse which influences the addressing stability. Then the effects of the slope ratio of the linear falling ramp reset pulse on the addressing voltage and addressing time were investigated. The experimental results show that the minimum addressing voltage increases with the increase of the slope ratio of the falling ramp reset pulse, and so does the minimum addressing time. Based on the experimental results, the optimization of the addressing time and the slope ratio of the falling ramp pulse is discussed.展开更多
This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject c...This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets. The core circuit for charge/pulse conversion is specially optimized for low power, low noise and small area. An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification. The measurement result shows a standard deviation of 1.8 LSB for full-scale output. The ADC has an area of 45 × 45μm^2 and consumes less than 2 μW in a standard 1P-6M 0.18μm CMOS process.展开更多
基金supported by the 2002 Ministry of Education Project for Science and Technology (2002,No.77)
文摘The effects of linear falling ramp reset pulse related to addressing operation in an alternating current plasma display panel （AC PDP） were studied. The wall charge waveforms were measured by the electrode balance method in a 12-inch coplanar AC PDP. The wall charge waveforms show the relationship between the slope ratio of the falling ramp reset pulse and the wall charges at the end of the falling ramp reset pulse which influences the addressing stability. Then the effects of the slope ratio of the linear falling ramp reset pulse on the addressing voltage and addressing time were investigated. The experimental results show that the minimum addressing voltage increases with the increase of the slope ratio of the falling ramp reset pulse, and so does the minimum addressing time. Based on the experimental results, the optimization of the addressing time and the slope ratio of the falling ramp pulse is discussed.
基金supported by the Major National Science & Technology Program of China(No.2012ZX03004004-002)
文摘This paper presents a 50 Hz 15-bit analog-to-digital converter （ADC） for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets. The core circuit for charge/pulse conversion is specially optimized for low power, low noise and small area. An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification. The measurement result shows a standard deviation of 1.8 LSB for full-scale output. The ADC has an area of 45 × 45μm^2 and consumes less than 2 μW in a standard 1P-6M 0.18μm CMOS process.
