针对图形处理芯片(GPU)中的曲面细分单元生成顶点数量过多的问题,提出一种基于三角形邻接关系的几何细分策略,称为TSTESS(Triangle Strip on Tessellation),其主要流程为,把细分块按照从外向内顺序拆分为多个环,对每个环生成多个梯形结...针对图形处理芯片(GPU)中的曲面细分单元生成顶点数量过多的问题,提出一种基于三角形邻接关系的几何细分策略,称为TSTESS(Triangle Strip on Tessellation),其主要流程为,把细分块按照从外向内顺序拆分为多个环,对每个环生成多个梯形结构,每个梯形生成大量连续的三角形,通过有限自动机根据三角形的绕向和相邻信息,提取出它们的共有顶点,构成连续的三角形条带并输出.TSTESS方法减少了顶点的生成数量,有利于后期的计算和存储.通过实验测试在各种细分参数的情况下,该方法生成的顶点数量只相当于传统的三角形列表方法的50%~65%左右,可提高细分单元的执行效率,并且易于使用硬件描述代码融入到已有的GPU设计中,便于曲面细分单元输出的三角形条带获得硬件加速.展开更多
A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test se...A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.展开更多
文摘针对图形处理芯片(GPU)中的曲面细分单元生成顶点数量过多的问题,提出一种基于三角形邻接关系的几何细分策略,称为TSTESS(Triangle Strip on Tessellation),其主要流程为,把细分块按照从外向内顺序拆分为多个环,对每个环生成多个梯形结构,每个梯形生成大量连续的三角形,通过有限自动机根据三角形的绕向和相邻信息,提取出它们的共有顶点,构成连续的三角形条带并输出.TSTESS方法减少了顶点的生成数量,有利于后期的计算和存储.通过实验测试在各种细分参数的情况下,该方法生成的顶点数量只相当于传统的三角形列表方法的50%~65%左右,可提高细分单元的执行效率,并且易于使用硬件描述代码融入到已有的GPU设计中,便于曲面细分单元输出的三角形条带获得硬件加速.
基金Sponsored by the National Natural Science Foundation of China(Grant No.61100031)the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.2015078)
文摘A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.
