针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from volta...The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.展开更多
为进一步提升HLS Ⅱ储存环光源的性能以及为未来实现top-off注入打下基础,研制了新的逐束团流强测量系统。系统硬件部分主要由ADC、FPGA和USB构成,采样精度高、架构简单、成本低。由于BPM和信号的峰值含有束团流强信息,该系统利用峰值...为进一步提升HLS Ⅱ储存环光源的性能以及为未来实现top-off注入打下基础,研制了新的逐束团流强测量系统。系统硬件部分主要由ADC、FPGA和USB构成,采样精度高、架构简单、成本低。由于BPM和信号的峰值含有束团流强信息,该系统利用峰值采样法测流强。在线测试结果表明,束流的纵向振荡对测量精度有较大影响,在开启纵向反馈抑制住纵向振荡时,该系统测量逐束团流强的精度较高,单束团流强的均方根误差值可达0.002 m A;关闭纵向反馈时,测量精度变差。该系统除了测量逐束团流强外,还实现了纵向工作点的测量,未来还可以测量逐束团寿命等,为合肥光源储存环性能提升,提供更多的束流诊断手段。展开更多
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
文摘The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.
文摘为进一步提升HLS Ⅱ储存环光源的性能以及为未来实现top-off注入打下基础,研制了新的逐束团流强测量系统。系统硬件部分主要由ADC、FPGA和USB构成,采样精度高、架构简单、成本低。由于BPM和信号的峰值含有束团流强信息,该系统利用峰值采样法测流强。在线测试结果表明,束流的纵向振荡对测量精度有较大影响,在开启纵向反馈抑制住纵向振荡时,该系统测量逐束团流强的精度较高,单束团流强的均方根误差值可达0.002 m A;关闭纵向反馈时,测量精度变差。该系统除了测量逐束团流强外,还实现了纵向工作点的测量,未来还可以测量逐束团寿命等,为合肥光源储存环性能提升,提供更多的束流诊断手段。
