A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requiremen...A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.展开更多
A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump...A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University,China.
文摘A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.
基金supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469).
文摘A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.
