SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide(SiC) trench metal–oxide–semiconductor field-effect transistor(MOSFET) with a dual shield gate(DSG) and optimized junction field-effect transistor(JFET) layer(ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area(SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET(Con-ATMOS), the specific on-resistance(Ron,sp) is significantly reduced at almost the same avalanche breakdown voltage(BVav). Moreover, the DSG structure brings about much smaller reverse transfer capacitance(Crss) and input capacitance(Ciss), which helps to reduce the gate–drain charge(Qgd) and gate charge(Qg). Therefore, the high frequency figure of merit(HFFOM) of Ron,sp·Qgdand Ron,sp· Qgfor the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively.The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current(Id,sat) at a gate voltage(Vgs) of 15 V for the ODSGTMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate(SG) at a large drain voltage. With the reduced Id,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

On-State Breakdown Model for High Voltage RESURF LDMOS

An analytical breakdown model under on state condition for high voltage RESURF LDMOS is proposed.The model considers the drift velocity saturation of carriers and influence of parasitic bipolar transistor.As a result,electric field profile of n drift in LDMOS at on state is obtained.Based on this model,the electric SOA of LDMOS can be determined.The analytical results partially fit to our numerical (by MEDICI) and experiment results.This model is an aid to understand the device physics during on state accurately and it also directs high voltage LDMOS design.

Kirk effect and suppression for 20 V planar active-gap LDMOS

For 20 V planar active-gap lateral double-diffused MOSFET （LDMOS）, the sectional channel is utilized to decrease the electric field in the n-drift region below the poly gate edge in the off-state, compared with the conventional single channel. Then the n-drift concentration can be increased to decrease the Kirk effect, while keeping off-state breakdown voltage Vbd unchanged. Meanwhile the influence of the n-drift concentration and the n-drift length Ldrift （the drain n＋ diffusion to gate spacing） which are related to the Kirk effect is discussed. The trade-offs between Rdson.Area, breakdown voltage Vbd and the electrical safe operating area （e-SOA） performance of LDMOS are considered also. Finally the proposed planar active-gap LDMOS devices with varied values of Ldria are experimentally demonstrated. The experimental results show that the Kirk effect can be greatly suppressed with slight increase in the Rdson.Area parameter.

Energy capability enhancement for isolated extended drain NMOS transistors

Isolated extended drain NMOS（EDNMOS） transistors are widely used in power signal processing.The hole current induced by a high electric field can result in a serious reliability problem due to a parasitic NPN effect. By optimizing p-type epitaxial（p-epi） thickness,n-type buried layer（BLN） and nwell doping distribution,the peak electric field is decreased by 30%and the peak hole current is decreased by 60%,which obviously suppress the parasitic NPN effect.Measured I-V characteristics and transmission line pulsing（TLP） results show that the onstate breakdown voltage is increased from 28 to 37 V when 6 V Vgs is applied and the energy capability is improved by about 30%,while the on-state resistance remains unchanged.

An LDMOS with large SOA and low specific on-resistance

An LDMOS with nearly rectangular-shape safe operation area （SOA） and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be low- ered down to 74.7 m^2.cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ion- ization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large V6s is obtained and snap-back is suppressed as well.