Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

A Novel Full Differential Feedforward Fourth-Order Bandpass Sigma-Delta Modulator

In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency （IF） receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-μm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.

基于∑-△M的五阶MFLR数字微加速度计闭环控制系统

为了进一步抑制加速度计信号带宽范围内的噪声,提出并设计了一种基于∑-△M的五阶多反馈谐振式（MFLR）微机械加速度计闭环控制系统,该系统通过增加额外的内部负反馈对量化噪声进行再一次整形.微机械加速度计结构为一种全差分式结构,在结构层厚度为60 μm、基底层厚度为400μm的SOI硅片上,经过光刻、溅射、深度反应离子刻蚀等工艺步骤加工而成.整个闭环控制系统的Matlab/Simulink模型首先被建立,然后采用“单位圆分析法”进行系统参数的设定,系统仿真显示：当输入幅值1gn、频率128Hz的加速度信号时,加速度计的噪声为-136.2 dB,与传统五阶MF结构的∑-△M闭环控制系统相比,在0 ～500 Hz信号带宽范围内的噪声降低了7.9dB.最后整个系统在四层PCB电路板上进行了功能性验证和测试.

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.

A 2.52-mW continuous-time Σ△ modulator with 72 dB dynamic range for FM radio

A continuous-time ∑△ modulator with a third-order loop filter and a 3-bit quantizer is realized. The modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator, an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.

New Blind Recognition Method of SCLD and OFDM in Alpha-Stable Noise

This paper deals with modulation classification under the alpha-stable noise condition. Our goal is to discriminate orthogonal frequency division multiplexing (OFDM) modulation type from single carrier linear digital (SCLD) modulations in this scenario. Based on the new results concerning the generalized cyclostationarity of these signals in alpha-stable noise which are presented in this paper, we construct new modulation classification features without any priori information of carrier frequency and timing offset of the received signals, and use support vector machine (SVM) as classifier to discriminate OFDM from SCLD. Simulation results show that the recognition accuracy of the proposed algorithm can be up to 95% when the mix signal to noise ratio (MSNR) is up to ?1 dB.

A 4 GHz CMOS multiplier for sigma–delta modulated signals

An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA current from a 2.8 V supply.The silicon area occupied without PADs is 1.17 mm;.

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer＇s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer＇s integrated phase noise is less than 1°（1 kHz to 100 MHz）with a 4.375 GHz carrier（after divide-by-2）,and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.