Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

Novel modified min-sum decoding algorithm for low-density parity-check codes

The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

5GNR系统中的LDPC编译码技术

低密度检验码作为时下最流行的前向纠错码之一,在5G通信系统中占据绝对重要的位置。随机构造的LDPC(Low Density Parity Check Code)虽然具有极佳的性能,但是运算复杂度过高,工业应用价值不高,与之相对比的,准循环构造的LDPC码在性能和运算复杂度上做了适度的折衷,保证了LDPC硬件可实现性的同时满足了一定的性能需求,在5G的三大应用场景下都有很好的表现,满足了e MBB(enhanced Mobile Broadband,增强移动宽带)场景下对系统吞吐率和峰值速率的需求、mMTC(massive Machine Type Communications,大规模机器通信)场景下对连接数量的需求以及uRLLC(ultra Reliable Low Latency Communications,超高可靠低时延通信)场景下对端到端时延的需求。为了验证LDPC在5G NR系统中的性能,追踪了5G NR协议内物理层LDPC编译码的流程,包括CRC校验模块、信道编码模块和速率适配模块。也探讨了LDPC译码算法的演变过程,并着重分析了最小和算法的应用和修正。

Path planning of a free-floating space robot based on the degree of controllability

An effective and more efficient path planning algorithm is developed for a kinematically non-redundant free-floating space robot(FFSR) system by proposing a concept of degree of controllability(DOC) for underactuated systems. The DOC concept is proposed for making full use of the internal couplings and then achieving a better control effect, followed by a certain definition of controllability measurement which measures the DOC, based on obtaining an explicit and finite equivalent affine system and singular value decomposition. A simple method for nilpotent approximation of the Lie algebra generated by the FFSR system is put forward by direct Taylor expansion when obtaining the equivalent system. Afterwards, a large-controlla- bility-measurement(LCM) nominal path is searched by a weighted A* algorithm, and an optimal self-correcting method is designed to track the nominal path approximately, yielding an efficient underactuated path. The proposed strategy successfully avoids the drawback of inefficiency inherent in previous path-planning schemes, which is due to the neglect of internal couplings, and illustrative numerical examples show its efficacy.

An LDPC coded cooperative MIMO scheme over Rayleigh fading channels with unknown channel state information

This paper describes a coded cooperative multiple-input multiple-output(MIMO) scheme,where structured low-density parity-check(LDPC) codes belonging to a family of repeat-accumulate(RA) codes are employed.The outage probability of the scheme over Rayleigh fading channels is deduced.In an unknown channel state information(CSI) scenario,adaptive transversal filters based on a spatio-temporal recursive least squares(ST-RLS) algorithm are adopted in the destination to realize receive diversity gain.Also,a joint 'Min-Sum' iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the bilayer Tanner graph that can be used to fully characterize two distinct structured LDPC codes employed by the source and relay.Simulation results verify the effectiveness of the adopted filter in the coded cooperative MIMO scheme.Theoretical analysis and numerical simulations show that the LDPC coded cooperative MIMO scheme can well combine cooperation diversity,multi-receive diversity,and channel coding gains,and clearly outperforms coded noncooperation schemes under the same conditions.

Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.