Formation of the intermediate semiconductor layer for the Ohmic contact to silicon carbide using Germanium implantation

By formation of an intermediate semiconductor layer （ISL） with a narrow band gap at the metallic contact/SiC interface, this paper realises a new method to fabricate the low-resistance Ohmic contacts for SiC. An array of transfer length method （TLM） test patterns is formed on N-wells created by P＋ ion implantation into Si-faced p-type 4H- SiC epilayer. The ISL of nickel-metal Ohmic contacts to n-type 4H-SiC could be formed by using Germanium ion implantation into SiC. The specific contact resistance pc as low as 4.23×10-5Ω·cm2 is achieved after annealing in N2 at 800 ℃ for 3 min, which is much lower than that （〉 900℃） in the typical SiC metallisation process. The sheet resistance Rsh of the implanted layers is 1.5 kΩ/□. The technique for converting photoresist into nanocrystalline graphite is used to protect the SiC surface in the annealing after Ge＋ ion implantations.

Express Methods for Measurement of Electroconductivity of Semiconductor Layered Crystal

We describe theoretically the grounded method of measuring the conductivity of anisotropic layered semiconductor materials. The suggested method implies the use of a four-probe testing device with a linear arrangement of probes. The final expressions for identifying the electrical conductivity are presented in the form of a series of analytic functions. The suggested method is experimentally verified, and practical recommendations of how to apply it are also provided.

Valley polarization in transition metal dichalcogenide layered semiconductors:Generation,relaxation,manipulation and transport

In recent years,valleytronics researches based on 2D semiconducting transition metal dichalcogenides have attracted considerable attention.On the one hand,strong spin–orbit interaction allows the presence of spin–valley coupling in this system,which provides spin addressable valley degrees of freedom for information storage and processing.On the other hand,large exciton binding energy up to hundreds of me V enables excitons to be stable carriers of valley information.Valley polarization,marked by an imbalanced exciton population in two inequivalent valleys(+K and-K),is the core of valleytronics as it can be utilized to store binary information.Motivated by the potential applications,we present a thorough overview of the recent advancements in the generation,relaxation,manipulation,and transport of the valley polarization in nonmagnetic transition metal dichalcogenide layered semiconductors.We also discuss the development of valleytronic devices and future challenges in this field.

Comparative coherence between layered and traditional semiconductors: unique opportunities for heterogeneous integration

As Moore’s law deteriorates,the research and development of new materials system are crucial for transitioning into the post Moore era.Traditional semiconductor materials,such as silicon,have served as the cornerstone of modern technologies for over half a century.This has been due to extensive research and engineering on new techniques to continuously enrich silicon-based materials system and,subsequently,to develop better performed silicon-based devices.Meanwhile,in the emerging post Moore era,layered semiconductor materials,such as transition metal dichalcogenides(TMDs),have garnered considerable research interest due to their unique electronic and optoelectronic properties,which hold great promise for powering the new era of next generation electronics.As a result,techniques for engineering the properties of layered semiconductors have expanded the possibilities of layered semiconductor-based devices.However,there remain significant limitations in the synthesis and engineering of layered semiconductors,impeding the utilization of layered semiconductor-based devices for mass applications.As a practical alternative,heterogeneous integration between layered and traditional semiconductors provides valuable opportunities to combine the distinctive properties of layered semiconductors with well-developed traditional semiconductors materials system.Here,we provide an overview of the comparative coherence between layered and traditional semiconductors,starting with TMDs as the representation of layered semiconductors.We highlight the meaningful opportunities presented by the heterogeneous integration of layered semiconductors with traditional semiconductors,representing an optimal strategy poised to propel the emerging semiconductor research community and chip industry towards unprecedented advancements in the coming decades.

Measurement of residual stress in a multi-layer semiconductor heterostructure by micro-Raman spectroscopy

Si-based multilayer structures are widely used in current microelectronics. During their preparation, some inhomogeneous residual stress is induced, resulting in competition between interface mismatching and surface energy and even leading to structure failure. This work presents a methodological study on the measurement of residual stress in a multi-layer semiconductor heterostructure. Scanning electron microscopy（SEM）, micro-Raman spectroscopy（MRS）, and transmission electron microscopy（TEM） were applied to measure the geometric parameters of the multilayer structure. The relationship between the Raman spectrum and the stress/strain on the [100] and [110] crystal orientations was determined to enable surface and crosssection residual stress analyses, respectively. Based on the Raman mapping results, the distribution of residual stress along the depth of the multi-layer heterostructure was successfully obtained.

Transforming a Two-Dimensional Layered Insulator into a Semiconductor or a Highly Conductive Metal through Transition Metal Ion Intercalation

Atomically thin two-dimensional(2D) materials are the building bricks for next-generation electronics and optoelectronics, which demand plentiful functional properties in mechanics, transport, magnetism and photoresponse.For electronic devices, not only metals and high-performance semiconductors but also insulators and dielectric materials are highly desirable. Layered structures composed of 2D materials of different properties can be delicately designed as various useful heterojunction or homojunction devices, in which the designs on the same material(namely homojunction) are of special interest because preparation techniques can be greatly simplified and atomically seamless interfaces can be achieved. We demonstrate that the insulating pristine ZnPS_3, a ternary transition-metal phosphorus trichalcogenide, can be transformed into a highly conductive metal and an n-type semiconductor by intercalating Co and Cu atoms, respectively. The field-effect-transistor(FET) devices are prepared via an ultraviolet exposure lithography technique. The Co-ZnPS_3 device exhibits an electrical conductivity of 8 × 10^(4) S/m, which is comparable to the conductivity of graphene. The Cu-ZnPS_3 FET reveals a current ON/OFF ratio of 1-05 and a mobility of 3 × 10^(-2 )cm^(2)·V^(-1)·s^(-1). The realization of an insulator, a typical semiconductor and a metallic state in the same 2D material provides an opportunity to fabricate n-metal homojunctions and other in-plane electronic functional devices.

Anti-Fowler Temperature Regime in Photoemission from <i>n</i>-Type Semiconductors with Surface Accumulation Layer

According to the Fowler theory and numerous experiments the quantum efficiency for photoemission from conductors increases with temperature. Here we show that an opposite temperature dependence is also possible, when the photoemission is from quasi-metallic surface accumulation layers of n-type semiconductors. This is due to the temperature dependence of the Fermi level energy in semiconductors. The Fermi level energy increases with decreasing temperature;this leads to a decrease of the semiconductor work function and consequently an increase of the quantum efficiency photoemission at constant value of absorbed light quanta of energy. We have calculated this effect for electron accumulation layer in n-GaN, induced by adsorption of positively charged cesium or barium ions. It is found that at low temperatures near liquid nitrogen, the quantum efficiency for photoemission increases to near 55%, which is comparable to the largest values, reported for any known photo-ca-thodes. This phenomenon may prove useful for efficient photo-cathodes operating at low temperatures.

非层状二维CdSe的制备及厚度对带隙的影响

二维半导体材料的天然带隙有望弥补石墨烯的零带隙缺陷,打破后者在场效应晶体管、开关器件、逻辑电路等领域的应用瓶颈. 相较于层状半导体材料,非层状半导体材料多以较强的离子键/共价键结合,且各向同性,因此要获取其二维结构存在一定挑战. 本论文通过化学气相沉积法实现了非层状CdSe在云母衬底上的二维各向异性生长. 详细表征了二维CdSe的微观形貌、晶体结构和光学特性等. 结果表明,样品具有显著的光致发光 (PL )效应,说明厚度减薄至纳米级时不会破坏CdSe的直接带隙属性. 此外,随着厚度减小,样品的PL峰逐渐蓝移. 为了进一步解释该现象,采用基于密度泛函理论的第一性原理计算方法,研究了不同厚度的CdSe的能带结构,结果显示均为直接带隙,且随厚度减小,带隙值增大,与实验现象吻合. 由此可知,通过生长参数调控二维CdSe的厚度,即可实现对其带隙的有效调控,这对相关光电器件的性能提升具有指导意义.

p型InGaAs薄层半导体欧姆接触特性分析

从电流在金属和半导体界面的拥堵效应出发,依据圆形传输线模型(CTLM)推导出适用于金属和薄层半导体间欧姆接触电阻率的表达式。利用四探针电阻测量法、高导电性下小电流密度测试法以及对薄膜电阻和传输线长度采用非线性拟合的方法获得薄层半导体与金属之间高精度的欧姆接触电阻和电阻率测试结果。研究了Zn掺杂浓度和合金温度对p型InGaAs薄层半导体欧姆接触特性的影响。研究发现:在相同合金温度下,掺杂浓度为1.94×10^(19)cm^(-3)时,样品的欧姆接触电阻率小于掺杂浓度为1.52×10^(19)cm^(-3)的样品,即提高p型InGaAs薄层半导体Zn掺杂浓度有利于半导体和金属Ti/Pt/Au形成良好的欧姆接触;相同Zn掺杂浓度的p型InGaAs薄层半导体,在经过光刻、等离子体去胶、湿法腐蚀等前道工艺后,合金温度为410℃的样品欧姆接触电阻率小于合金温度为380℃的样品,即可通过提高合金温度改善半导体与金属之间的欧姆接触特性。

Zn杂质诱导GaInP/AlGaInP红光半导体激光器量子阱混杂的研究

在GaAs基GaInP/AlGaInP单量子阱结构外延片上分别使用磁控溅射设备生长ZnO薄膜和等离子增强化学气相沉积设备生长SiO2薄膜,以ZnO介质层作为Zn杂质诱导源,采用固态扩Zn的方式对激光器进行选择性区域诱导以制备非吸收窗口来提高器件的腔面光学灾变损伤阈值,从而提高半导体激光器的输出功率和长期可靠性。在580~680℃、20~60 min退火条件下对Zn杂质诱导量子阱混杂展开研究,实验发现,ZnO/SiO2或ZnO/Si3N4复合介质层的采用比单一Zn介质层的杂质诱导蓝移量大,且在680℃、30 min的条件下获得了最大55 nm的蓝移量。分析结果表明,介质层所施加的压应变会将外延片表面GaAs层中Ga原子析出,促使Zn原子进入外延层中以诱导量子阱混杂。通过测量光致发光光谱发现发光强度并没有明显下降,可为后期器件制作提供借鉴。

Ⅲ族氮化物半导体及其合金的原子层沉积和应用

Ⅲ族氮化物半导体由于包含了宽的直接禁带宽度、高击穿场强、高电子饱和速度、高电子迁移率等优异的性质,自从发展以来便成为半导体领域中的一个热点.并且由于其禁带宽度可以从近紫外涵盖到红外区域,因此在传统半导体所难以实现的短波长光电子器件领域,也具有广阔的应用前景.原子层沉积由于其特殊的沉积机制可以在较低的温度下实现Ⅲ族氮化物半导体的高质量制备,通过调整原子层沉积的循环比也可以方便地调整合金材料中的成分.发展至今,原子层沉积已经成为制备Ⅲ族氮化物及其合金材料的一种重要方式.因此,本文着重介绍了近期使用原子层沉积进行Ⅲ族氮化物半导体及其合金的沉积及应用,包括使用不同前驱体、不同方式、不同类型原子层沉积,在不同温度、不同衬底上进行氮化物半导体及其合金的沉积.随后讨论了原子层沉积制备的Ⅲ族氮化物材料在不同器件中的应用.最后总结了原子层沉积在制备Ⅲ族氮化物半导体中的前景和挑战.

A NOVEL PHYSICAL-LAYER TRANSCEIVER USED IN USB2.0 SERIAL DATA LINK

The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.

Current spin polarization and spin injection efficiency in ZnO-based ferromagnetic semiconductor junctions

[FeNi（3 nm）/Zn1-xCoxO（3 nm）]2/ZnO（d nm）/[Zn1-xCoxO（3 nm）/Co（3 nm）]2 （d=3 and 10） semiconductor junctions were prepared by magnetron sputtering system and photolithography. The spin valve effect was observed in these junctions because the utility of the ferromagnetic composite layers acted as soft and hard magnetic layers. The electrical detection was performed by measuring the magnetoresistance of these junctions to investigate the current spin polarization asc in the ZnO layer and the spin injection efficiency η of spin-polarized electrons. asc was reduced from 11.7% （and 10.5%） at 90 K to 7.31% （and 5.93%） at room temperature for d=3 （and d=10）. And η was reduced from 39.5% （and 35.5%） at 90 K to 24.7% （and 20.0%） at room temperature for d=3 （and d=10）.

Direct Structural Evidences of Epitaxial Growth Ge<SUB>1-X</SUB>Mn<SUB>X</SUB>Nanocolumn Bi-Layers on Ge(001)

Molecular Beam Epitaxy (MBE) system equipped with in-situ Reflection High-Energy Electron Diffraction (RHEED) has been used for (Ge, Mn) thin film growth and monitoring the surface morphology and crystal structure of thin films. Based on the observation of changes in RHEED patterns during nanocolumn growth, we used a real-time control approach to realize multilayer structures that consist of two nanocolumn layers separated by a Ge barrier layer. Transmission Electron Microscopy (TEM) has been used to investigate the structural properties of the GeMn nanocolumns and GeMn/Ge nanocolumns bi-layers samples.

Application of an Al-doped zinc oxide subcontact layer on vanadium-compensated 6H–SiC photoconductive switches

Al-doped ZnO thin film （AZO） is used as a subcontact layer in 6H-SiC photoconductive semiconductor switches （PCSSs） to reduce the on-state resistance and optimize the device structure. Our photoconductive test shows that the onstate resistance of lateral PCSS with an n＋-AZO subcontact layer is 14.7% lower than that of PCSS without an n＋-AZO subcontact layer. This occurs because a heavy-doped AZO thin film can improve Ohmic contact properties, reduce contact resistance, and alleviate Joule heating. Combined with the high transparance characteristic at 532 nm of AZO film, vertical structural PCSS devices are designed and their structural superiority is discussed. This paper provides a feasible route for fabricating high performance SiC PCSS by using conductive and transparent ZnO-based materials.

A study of GaN MOSFETs with atomic-layer-deposited Al_2O_3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors （MOSFETs） with atomic-layer- deposited A1203 gate dielectrics are fabricated. The device, with atomic-layer-deposited A1203 as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al203 as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the A1203 film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm^2/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition A1203 growth and device fabrication.

Electrical Characterization of Semiconductor Diode Using Alternating Signal Measurements at Forward Bias

The general analysis of the forward AC behavior of a semiconductor diode under series mode is pre- sented for the first time.A new method without any particular assumption to characterize a diode was developed. This method can accurately measure the dependence of series resistance, junction capacitance, junction vol- tage, ideality factor, and interfacial layer impedance on forward biases. The measurements confirm that the ne- gative capacitance (NC) of Schottky diode is an effect of the junction, and the interfacial layer can be consi- dered as a layer structure with nonlinear resistance and capacitance.

Impacts of Temperature and Frequency on the Dielectric Properties for Insight into the Nature of the Charge Transports in the Tl2S Layered Single Crystals

Investigation of the electric properties of semi-conducting materials in an applied ac electric fields gives information about the nature of charge transport and localized states in the forbidden gap. Layered crystals usually contain structural defects, such as dislocations and vacancies that may form a high density of localized states near the Fermi level. So, the current study was carried out for insight into the dielectric Properties of Tl2S layered single crystals. These properties were studied using the ac measurements in the low temperatures ranging from 77 to 300 K. The real part of dielectric constant ε?, imaginary part of dielectric constant ε?, the dissipation factor tan δ and the alternating current conductivity σac were measured in an applied ac electric field of frequencies extending from 2.5 to 50 kHz. Based on the dependencies of these dielectric parameters on both the frequency and temperature, the dielectric properties of the crystals under investigation were elucidated and analyzed. The ac conductivity was found to obey the power law σac(ω) = Aωs with which the values of the exponent s were evaluated to be less than unity in the range 0.21 ≥ s ≥ 0.19. Furthermore, it was found that the temperature dependence of ac conductivity follows the Arrhenius relation via which the impact of temperature on the electrical processes in an applied ac electric field was illustrated and analyzed. The influences of temperature and frequency on both the exponent s and band gap were also discussed in this investigation.