The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memo...The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.展开更多
The growth in wireless technologies applications makes the necessity of providing a reliable communication over wireless networks become obvious.Guaranteeing real time communication in wireless medium poses a signific...The growth in wireless technologies applications makes the necessity of providing a reliable communication over wireless networks become obvious.Guaranteeing real time communication in wireless medium poses a significant challenge due to its poor delivery reliability.In this study,a recovery and redundancy model based on sequential time division multiple access(S-TDMA)for wireless communication is developed.The media access control(MAC)layer of the S-TDMA determines which station should transmit at a given time slot based on channel state of the station.Simulations of the system models were carried out using MATLAB SIMULINK software.SIMULINK blocks from the signal processing and communication block sets were used to model the communication system.The S-TDMA performance is evaluated with total link reliability,system throughput,average probability of correct delivery before deadline and system latency.The evaluation results displayed in graphs when compared with instant retry and drop of frame were found to be reliable in recovering loss packets.展开更多
文摘The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.
文摘The growth in wireless technologies applications makes the necessity of providing a reliable communication over wireless networks become obvious.Guaranteeing real time communication in wireless medium poses a significant challenge due to its poor delivery reliability.In this study,a recovery and redundancy model based on sequential time division multiple access(S-TDMA)for wireless communication is developed.The media access control(MAC)layer of the S-TDMA determines which station should transmit at a given time slot based on channel state of the station.Simulations of the system models were carried out using MATLAB SIMULINK software.SIMULINK blocks from the signal processing and communication block sets were used to model the communication system.The S-TDMA performance is evaluated with total link reliability,system throughput,average probability of correct delivery before deadline and system latency.The evaluation results displayed in graphs when compared with instant retry and drop of frame were found to be reliable in recovering loss packets.
